Patents by Inventor Thomas J. Bardsley
Thomas J. Bardsley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7852151Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: GrantFiled: May 30, 2008Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nickolls
-
Patent number: 7659740Abstract: Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal.Type: GrantFiled: August 11, 2008Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
-
Publication number: 20090027075Abstract: A circuit and method of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention comprises a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: ApplicationFiled: August 11, 2008Publication date: January 29, 2009Applicant: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
-
Patent number: 7466156Abstract: A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.Type: GrantFiled: March 25, 2004Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Joseph O. Marsh, Jeremy Stephens, Charlie C. Hwang, James S. Mason, Huihao Xu, Matthew B. Baecher, Thomas J. Bardsley, Mark R. Taylor
-
Publication number: 20080284517Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: ApplicationFiled: May 30, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
-
Patent number: 7397302Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: GrantFiled: April 13, 2007Date of Patent: July 8, 2008Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
-
Patent number: 7250814Abstract: A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages (201, 202) connected in parallel with each amplifier stage having a gain control means. Input signal means (203, 204) are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage (216) are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (212).Type: GrantFiled: April 1, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Matthew R. Cordrey-Gale, James S. Mason, Philip J. Murfet, Gareth J. Nicholls
-
Patent number: 6834365Abstract: An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.Type: GrantFiled: July 17, 2001Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Robert M. Bunce, Timothy M. Kemp, Brian J. Schuh
-
Publication number: 20030018929Abstract: An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.Type: ApplicationFiled: July 17, 2001Publication date: January 23, 2003Applicant: International Business Machines CorporationInventors: Thomas J. Bardsley, Robert M. Bunce, Timothy M. Kemp, Brian J. Schuh
-
Patent number: 6094056Abstract: A test fixture for use with an improved multi-chip-module wherein the multi-chip-module has a plurality of chips on the top surface, the module having at least one net associated with the chips completely embedded within the substrate and wherein at least one pad is attached to the bottom surface of the substrate and a conductive path provided between the pad and the net. The test fixture includes a zero-insertion-force socket having at least one socket pin having a surface for conductively contacting the pad on the multi-chip-module and extending through the socket and a circuit board having a plurality of inlets for conductively receiving the socket pins including the socket pin contacting the pad.Type: GrantFiled: March 5, 1998Date of Patent: July 25, 2000Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Jed R. Eastman
-
Patent number: 5754410Abstract: An improved multi-chip-module having a substrate having top and bottom surfaces, a plurality of chips on the top surface, a plurality of pins on the bottom surface, each chip having at least one lead extending through the substrate and conductively coupled to a corresponding pin, the module having at least one net associated with the chips and completely embedded within the substrate, the improvement comprising at least one pad attached to the bottom surface of the substrate, and a conductive path conductively coupled between the pad and the net.Type: GrantFiled: September 11, 1996Date of Patent: May 19, 1998Assignee: International Business Machines CorporationInventors: Thomas J. Bardsley, Jed R. Eastman