Patents by Inventor Thomas J. Giovannini
Thomas J. Giovannini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20170200489Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: January 13, 2017Publication date: July 13, 2017Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Patent number: 9665507Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.Type: GrantFiled: May 11, 2011Date of Patent: May 30, 2017Assignee: Rambus Inc.Inventors: Ian Shaeffer, Thomas J. Giovannini
-
Patent number: 9552865Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: November 3, 2015Date of Patent: January 24, 2017Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20160293239Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.Type: ApplicationFiled: April 4, 2016Publication date: October 6, 2016Inventors: Thomas J. Giovannini, Catherine Chen, Scott C. Best, John Eric Linstadt, Frederick A. Ware
-
Publication number: 20160239208Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.Type: ApplicationFiled: February 2, 2016Publication date: August 18, 2016Inventors: Thomas J. Giovannini, John Eric Linstadt
-
Publication number: 20160125930Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: November 3, 2015Publication date: May 5, 2016Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Patent number: 9298228Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.Type: GrantFiled: July 27, 2015Date of Patent: March 29, 2016Assignee: Rambus Inc.Inventors: Abhijit M. Abhyankar, Ravindranath Kollipara, Thomas J. Giovannini, Ming Li, David A. Secker, Arun Vaidyanath, Donald R. Mullen, Adrian F. Torres
-
Patent number: 9263103Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: March 17, 2008Date of Patent: February 16, 2016Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20150331732Abstract: An integrated circuit memory device is disclosed. The memory device includes at least one group of storage cells. Logic derives a count of error code correction events for each of the at least one group of storage cells. Storage stores the count. A memory control interface selectively communicates the count to a memory controller.Type: ApplicationFiled: May 8, 2015Publication date: November 19, 2015Applicant: Rambus Inc.Inventors: Thomas J. Giovannini, Kurt T. Knorpp
-
Patent number: 9177632Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 18, 2015Date of Patent: November 3, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Patent number: 9165638Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 1, 2015Date of Patent: October 20, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Patent number: 9141472Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.Type: GrantFiled: September 11, 2012Date of Patent: September 22, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Ian Shaeffer
-
Patent number: 9142281Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: April 28, 2015Date of Patent: September 22, 2015Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20150255144Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: April 28, 2015Publication date: September 10, 2015Applicant: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20150248926Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: May 18, 2015Publication date: September 3, 2015Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20150243343Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: May 1, 2015Publication date: August 27, 2015Applicant: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20130086449Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.Type: ApplicationFiled: September 11, 2012Publication date: April 4, 2013Applicant: RAMBUS INC.Inventors: Thomas J. Giovannini, Ian Shaeffer
-
Patent number: 8407441Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: GrantFiled: May 19, 2011Date of Patent: March 26, 2013Assignee: Rambus Inc.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
-
Publication number: 20120023363Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.Type: ApplicationFiled: May 11, 2011Publication date: January 26, 2012Applicant: RAMBUS INC.Inventors: Ian Shaeffer, Thomas J. Giovannini
-
Publication number: 20110216611Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.Type: ApplicationFiled: May 19, 2011Publication date: September 8, 2011Applicant: RAMBUS INC.Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo