Patents by Inventor Thomas J. Griffin
Thomas J. Griffin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11158394Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: April 2, 2020Date of Patent: October 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Publication number: 20200234783Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: ApplicationFiled: April 2, 2020Publication date: July 23, 2020Inventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 10658059Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: October 14, 2016Date of Patent: May 19, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 10585858Abstract: Log synchronization among discrete devices in a computer system includes, periodically at a predefined interval: sending, by a host to each of a plurality of discrete devices in the computer system, a synchronization tag, wherein each of the discrete devices, responsive to receiving the synchronization tag from the host, is configured to record the synchronization tag in a log entry; and recording, by the host, the synchronization tag in a log entry.Type: GrantFiled: February 18, 2016Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Patent number: 10223372Abstract: Log synchronization among discrete devices in a computer system includes, periodically at a predefined interval: sending, by a host to each of a plurality of discrete devices in the computer system, a synchronization tag, wherein each of the discrete devices, responsive to receiving the synchronization tag from the host, is configured to record the synchronization tag in a log entry; and recording, by the host, the synchronization tag in a log entry.Type: GrantFiled: January 26, 2016Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Patent number: 10115472Abstract: A data storage system includes a non-volatile memory array controlled by a controller. In response to receipt of write data to be written to the non-volatile memory array, the controller determines whether a read count of an unfinalized candidate block of storage within the non-volatile memory array satisfies a read count threshold applicable to the block. In response to determining that the read count of the unfinalized candidate block satisfies the read count threshold, the controller finalizing programming of the candidate block and programming an alternative block with the write data.Type: GrantFiled: August 2, 2017Date of Patent: October 30, 2018Assignee: International Business Machines CorporationInventors: Charles J. Camp, Timothy J. Fisher, Thomas J. Griffin, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Roman Pletka, Charalampos Pozidis, Gary A. Tressler, Sasa Tomic
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Patent number: 9934865Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: GrantFiled: February 3, 2017Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Patent number: 9934863Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PRI), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: GrantFiled: January 12, 2017Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170212908Abstract: Log synchronization among discrete devices in a computer system includes, periodically at a predefined interval: sending, by a host to each of a plurality of discrete devices in the computer system, a synchronization tag, wherein each of the discrete devices, responsive to receiving the synchronization tag from the host, is configured to record the synchronization tag in a log entry; and recording, by the host, the synchronization tag in a log entry.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Inventors: THOMAS J. GRIFFIN, STEVEN J. HNATKO
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Publication number: 20170212946Abstract: Log synchronization among discrete devices in a computer system includes, periodically at a predefined interval: sending, by a host to each of a plurality of discrete devices in the computer system, a synchronization tag, wherein each of the discrete devices, responsive to receiving the synchronization tag from the host, is configured to record the synchronization tag in a log entry; and recording, by the host, the synchronization tag in a log entry.Type: ApplicationFiled: February 18, 2016Publication date: July 27, 2017Inventors: THOMAS J. GRIFFIN, STEVEN J. HNATKO
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Patent number: 9691488Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PRI), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: GrantFiled: March 9, 2016Date of Patent: June 27, 2017Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170169890Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: ApplicationFiled: December 15, 2015Publication date: June 15, 2017Inventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170169893Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PRI), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: ApplicationFiled: January 12, 2017Publication date: June 15, 2017Inventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170169894Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: ApplicationFiled: February 3, 2017Publication date: June 15, 2017Inventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170169891Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PRI), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: ApplicationFiled: March 9, 2016Publication date: June 15, 2017Inventors: Thomas J. Griffin, Steven J. Hnatko
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Patent number: 9659664Abstract: A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE.Type: GrantFiled: December 15, 2015Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Thomas J. Griffin, Steven J. Hnatko
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Publication number: 20170032847Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: ApplicationFiled: October 14, 2016Publication date: February 2, 2017Inventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9524800Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.Type: GrantFiled: September 26, 2012Date of Patent: December 20, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9495287Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.Type: GrantFiled: September 26, 2012Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee
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Patent number: 9495289Abstract: Embodiments relate to solid state memory device including a storage array having a plurality of physical storage devices and the storage array includes a plurality of partitions. The solid state memory device also includes a controller comprising a plurality of mapping tables, wherein each of the plurality of mapping tables corresponds to one of the plurality of partitions. Each of the plurality of mapping tables is configured to store a physical location and a logical location of data stored in its corresponding partition.Type: GrantFiled: December 4, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas J. Griffin, Dustin J. VanStee