Abstract: A differential receiver circuit. In one embodiment, the circuit includes first and second input transistors, each having a first terminal coupled to a bias node (a first and second bias node, respectively), as well as first and second bias transistors, each having a first terminal coupled to the first and second bias nodes, respectively. The circuit further includes a first current source coupled to provide current to the first bias node and a second current source coupled to the second bias node. The differential receiver circuit is coupled to first and second, which receive first and second voltages, respectively. The first and second current sources provide current to the first and second bias nodes, respectively, such that the voltage present on the first and second bias nodes remains with approximately a threshold voltage of a midpoint between the voltages present on the first and second voltage nodes.

Abstract: In an integrated circuit carrier having a large number of power pins allocated to an internal power plane, the current flowing through the power pins may divide very unevenly, and result in current flow through some of the power pins which exceeds the maximum specification for either the package pin or for the socket into which the package may be inserted. In such a package, the magnitude of the current flowing through the highest current power pin may be reduced by configuring the resistance of the power plane(s) and vias to provide approximately the same total resistance to every power pin location. Slots may be cut in a package power plane to alter the current path and raise the impedance of the conduction path between some of the package power pins and the internal contact pads otherwise having the lowest impedance.

Abstract: An assembly of an optical interconnect module adaptable for mating with an optical connector having at least one optical fiber and an alignment pin.