Abstract: The present invention provides a method of manufacturing a semiconductor device. The method may include forming first and second adjacent tubs in an epitaxial layer, and simultaneously forming a base region in the first tub and lightly doped drain (LDD) regions in the second tub adjacent a first gate located over the second tub. The method may also include simultaneously forming a base contact region and a source/drain contact region.

Abstract: The present invention provides a bipolar transistor having a collector located in a semiconductor substrate having a given bandgap, and a base in contact with the collector. The base has a bandgap less than the bandgap of the substrate. In addition, the bipolar transistor further includes an emitter located over the base, where the emitter has a bandgap greater than the bandgap of the substrate. A method of forming a bipolar transistor, and an integrated circuit incorporating the bipolar transistor or the method, are also disclosed.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.

Abstract: An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer.

Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

Abstract: The specification describes a Schottky barrier device with a distributed guard ring where the guard ring is spaced from the barrier by an MOS gate so that the guard ring and barrier are connected at low bias by an inversion layer. According to the invention, the MOS gate is used to precisely space the guard ring from the Schottky barrier.

Abstract: The specification describes Schottky barrier devices with distributed guard rings. In one embodiment the guard ring only partially overlaps the barrier. In another embodiment the guard ring is spaced from the barrier throughout, but separated by an MOS gate so that the guard ring and barrier are connected at low bias by an inversion layer.