Abstract: A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers are disclosed. In one set of preferred embodiments, optical signals are conveyed between layers by respective vertical optical couplers disposed on the layers. In other preferred embodiments, optical signals are conveyed by stack optical waveguide coupling means. Yet other preferred embodiments have electrical via means formed in one or more layers to covey electrical signals between two or more layers.

Abstract: Three-dimensional opto-electronic modules having a plurality of opto-electronic (O/E) layers, with optical signals being routed between O/E layers within one or more three-dimensional volumes, are disclosed. In preferred embodiments, the O/E layers are disposed over and above one another with at least one of their edges aligned to one another. At least two of the O/E layers have waveguides with ends near the aligned edges. A plurality of Zconnector arrays are disposed between the O/E layers and within the three-dimensional volumes to provide a plurality of Zdirection waveguides. A first vertical optical coupler couples light from one waveguide in one O/E layer to a Z-direction waveguide, and a second vertical optical coupler couples the light from the Z-direction waveguide to a second waveguide in a second O/E layer. In further preferred embodiments, segments of the Z-connector arrays are held by a holding unit.

Abstract: Disclosed is device and/or material integration into thin opto-electronic layers, which increase room for chip-mounting, and reduce the total system cost by eliminating the difficulty of optical alignment between opto-electronic devices and optical waveguides. Opto-electronic devices are integrated with optical waveguides in ultra thin polymer layers on the order of 1 &mgr;m to 250 &mgr;m in thickness.

Abstract: A method for deplating defective capacitors comprising forming a plurality of capacitors on a semiconductor substrate, forming a plurality of metal contacts on the plurality of capacitors, and depositing a layer of photoresist on the semiconductor substrate. The photoresist layer is patterned so that the plurality of metal contacts are exposed, which are then contacted with an electrically conductive solution. The metal contacts, which are disposed over defective capacitors, are subsequently deplated. A method for forming a multi-chip module comprising forming a thin-film polymeric interconnect structure having a pair of sides, one of which is disposed on a silicon substrate having active or passive devices and the other of which has a computer chip mounted thereon. A multi-chip module formed by the method.

Abstract: Device modules with pins and methods for making device modules with pins are disclosed. One embodiment is directed to a method including forming a polymeric circuit structure having a first side and a second side on a substrate. The formed first side is adjacent to the substrate. A pin is bonded to the second side of the polymeric circuit structure. At least a portion of the substrate is removed to expose at least a portion of the first side of the polymeric circuit structure, and a device is mounted on the first side of the polymeric circuit structure.

Abstract: A package for a semiconductor device and a method for packaging a semiconductor device are disclosed. The semiconductor package uses a tape which allows for the production of packaged semiconductor devices having different contact patterns. The contact pattern is configured to the required pin contact pattern by varying the number and placement of balls on the bottom of the tape. In one embodiment, the tape includes bonding pads and an array of contact pads. Each bonding pad is connected to one of the contact pads, and an opening is disposed in the tape below each contact pad. A semiconductor device is connected to the tape and is electrically connected to the bonding pads. The semiconductor device is then sealed on the top and sides by a plastic top which attaches to the tape. Balls are then selectively attached to the tape such that they electrically connect to select contact pads so as to form a desired contact pattern.

Abstract: Opto-electrical systems having electrical and optical interconnections formed in thin layers with thin-film active devices are disclosed. In one embodiment, optical connections are made between the edge of one substrate and the surface of another substrate with the use of photorefractive materials. In another embodiment, the optical connection is made by separating a optical film from the first substrate and coupling the first substrate and the optical film to separate receptacles located on the second substrate. Film optical link modules employing aspects of the invention are also disclosed.

Abstract: Structures, methods and materials for making multilayer circuit substrates are disclosed. The structures include bumped structures or microencapsulated conductive particles suitable for use in a lamination process to make a multilayer printed circuit substrate.

Abstract: A test socket for ball grid array packages (BGA) for integrated circuits is described. The socket includes a basket or cradle shaped to receive the balls of the BGA in individual electrically conductive receptacles. The receptacles have flexible walls and an elastomer disposed outside the walls. The BGA, carrying the balls is urged in a direction parallel to the plane of the BGA thereby carrying the basket in the same direction. A stop is provided to limit the movement of the basket so that further movement of the BGA causes compression of the elastomer so as to provide an electrical connection between each ball and its associated receptacle despite any minor differences in the sizes or locations of the individual balls. Means are provided for connecting each of the receptacles to an external circuit.

Abstract: The ball bump structure of the subject invention provides a hermetically sealed bond pad at the surface of a semiconductor chip. An adhesion pad is formed at the surface of the bond pad. The adhesion pad includes a barrier layer, preferably a titanium/tungsten alloy, and a bonding layer, for example, a sputtered gold layer. A gold ball bump is formed on the adhesion pad. Methods for forming the improved structure herein are also disclosed.

Abstract: A semiconductor chip having a number of bonding pads on one face is mounted on a set of matching, mirror-image bonding pads on a packaging substrate, in a flip chip configuration. An alignment template is formed on and permanently secured to the substrate, and takes the form of a frame surrounding the substrate bonding pads. The height of the template is sufficient to receive the edges of the chip and hold the chip in place while the assembly is being transported to the soldering operation. No alignment operation is required, since the chip is merely placed in the receptacle formed by the template. The template is of course aligned with the substrate bonding pads when the template is created. The template can be formed on the substrate using photolithographic techniques, and, preferably, the template itself is formed of a photo-definable material.

Abstract: A high performance ball grid array is disclosed in which a ball grid array is modified to include a body having a recessed central cavity. The inclusion of a central cavity allows the die to be mounted on the same side of the package in which the solder balls are located. Since the die is mounted on the same side as that of the solder balls, only one set of leads is needed to electrically connect the die to the solder balls, thus requiring only one layer of electrically conductive material within the package, as opposed to conventional ball grid array packages which required two metal layers. In addition, since only one metal layer is needed, the present invention is able to operate without the use of electrically conductive vias. The die is connected via wire bonds to bonding areas located on the package. Each of the of bonding areas is substantially co-planar, and each bonding area is located at a different distance from one edge of the central cavity, thereby forming a staggered arrangement.

Abstract: A semiconductor chip having a number of bonding pads on one face is mounted on a set of matching, mirror-image bonding pads on a packaging substrate, in a flip chip configuration. An alignment template is formed on and permanently secured to the substrate, and takes the form of a frame surrounding the substrate bonding pads. The height of the template is sufficient to receive the edges of the chip and hold the chip in place while the assembly is being transported to the soldering operation. No alignment operation is required, since the chip is merely placed in the receptacle formed by the template. The template is of course aligned with the substrate bonding pads when the template is created. The template can be formed on the substrate using photolithographic techniques, and, preferably, the template itself is formed of a photo-definable material.