Abstract: A method for controlling the flow of semiconductor wafers within a semiconductor wafer processing facility. This method includes a wafer storage and preparation area (10) and a wafer metrology and etch area (12), both of which are monitored and/or controlled by a master controller (14). The wafer storage and preparation area (10) is typically kept at a class 10 clean room level and is comprised of a wafer storage area (16) and a wafer preparation area (18). The wafer metrology and etch area (12) is typically kept at a class 1000 clean room level and is comprised of an I/O cassette module (22), a wafer pre-aligner (24), a wafer router (26), a wafer metrology instrument (28), and a wafer etching instrument (30). The semiconductor wafers are transported, either manually or automatically, between the wafer storage area (16) and the wafer preparation area (18), as well as between the wafer storage and preparation area (10) and the wafer metrology and etch area (12), within wafer storage cassettes ( 20).

Abstract: A local area network interface for a network element having redundant processors is made by using a pair of connectors for each processor. A delay line is used between pairs of connectors for non-redundant LAN configurations. For redundant LANs, the delay line is not used.