Patents by Inventor Thomas J. Moloney

Thomas J. Moloney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6939784
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: September 6, 2005
    Assignee: Northrop Grumman Corporation
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Patent number: 6812558
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: November 2, 2004
    Assignee: Northrop Grumman Corporation
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Publication number: 20040191957
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Application
    Filed: April 9, 2004
    Publication date: September 30, 2004
    Applicant: NORTHROP GRUMMAN CORPORATION
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Publication number: 20040188821
    Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.
    Type: Application
    Filed: March 26, 2003
    Publication date: September 30, 2004
    Inventors: Li-Shu Chen, Philip C. Smith, Thomas J. Moloney, Howard Fudem
  • Patent number: D301811
    Type: Grant
    Filed: October 1, 1986
    Date of Patent: June 27, 1989
    Assignee: Alpine Engineered Products, Inc.
    Inventor: Thomas J. Moloney