Abstract: A dual privilege level coprocessor which is especially suited for use in a software asset protection system is described. The coprocessor includes a supervisor processing element and an application processing element. The supervisor processing element includes a supervisor processor and dedicated supervisor random access and read only memory. The application processing element includes an application processor, an application random access memory, a secure random access memory, a low privilege read only memory, and a high privilege read only memory. An internal bus couples the supervisor processor, application processor, high and low privilege random access memories, application random access memory and secure random access memory. The high privilege read only memory and the secure random access memory are enabled only in response to dedicated control signals from the supervisor processor.