Abstract: A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

Abstract: A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit.