Abstract: A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.

Abstract: A method and apparatus for unstacking registers in a data processing system (100). In one form, the present invention is a more time efficient solution to the problem of unstacking and stacking registers (154-158) during interrupt processing in a data processing system (100). By taking advantage of the fact that pulling a register value off of the stack does not change any of the values stored in the memory which is being used as the stack, the present invention reduces the unstacking and stacking each time that two interrupts are processed back to back with no non-interrupt processing in between. The present invention eliminates the unstacking of the program counter register (158) and the restacking of registers (154-158) by changing the value of the stack pointer register (161) without any corresponding stacking or unstacking operation.