Abstract: A lock detector for a phase locked loop circuit, wherein an oscillator is controlled by a control signal produced by comparing the output signal of the oscillator to a reference signal. The lock detector samples the control signal, examines a plurality of samples according to criteria associated with a prescribed lock condition between the reference signal and the oscillator output signal, and generates a lock signal indicative of the lock condition being met if the samples satisfy the criteria. In a favorable embodiment, the lock detector forms a first group of samples sampled at a rate controlled by the reference signal and a second group of samples sampled at a rate controlled by the oscillator output signal. The samples are stored and shifted at the respective rates in respective shift registers. The contents of each stage of the shift registers are then examined according to a logic function.

Abstract: A sensing circuit for a non-volatile memory operating from a supply voltage and comprising non-volatile memory cells and a non-volatile reference cell maintained in an un-programmed condition, the sensing circuit comprising means for determining the sensed current of a memory cell when accessed and comparing it with the reference current to determine whether the accessed memory cell is programmed or un-programmed. To allow opertion over a wide range of supply voltages, the sensing circuit comprises a scalable current mirror circuit connected to the reference and memory cells and providing a ratio, M, of reference current to sensed current that, in response to changes in the supply voltage, varies.