Abstract: A radar exciter including a direct digital synthesis (DDS) wideband waveform generator which performs the frequency synthesis function heretofore performed by a direct analog synthesizer. This is achieved by deriving the DDS frequencies, the exciter RF frequencies, the radar synchronizer clock frequency and receiver analog/digital (A/D) converter clock frequency from a common signal source generating a master frequency. The present invention eliminates the direct analog synthesizer and relies solely on the digital generation of waveforms by a DDS wideband waveform generator which performs a discrete sampling process so as to provide coherent frequency and timing relationships.

Abstract: A method of correcting phase and amplitude imbalances of I and Q components using digital correction coefficients. The amplitude Gc and phase coefficient Pc obtained solely in the time domain from a pilot signal. The I and Q components of the pilot signal are sampled over at least one integer cycle after which the number of samples taken during an integer number of cycles is determined for the samples of the component with the steepest slope. The sums of self and cross products are used to calculate the coefficients.

Abstract: An analog to digital converter system is disclosed as comprising a conversion circuit operative for developing a digital output corresponding to the magnitude of an input analog signal, a calibration port arranged for receiving digital calibration data from an external source, adjustable calibration circuitry associated with the conversion circuit, and an adjustment mechanism for adjusting the calibration circuitry in response to data applied to the calibration port.

Abstract: A method for distinguishing between multiple noise jammer sources having different noise modulation bandwidths. Noise signals are detected by a receiver having a bandwidth substantially the same as the bandwidth of the jammer noise source. The dwell time of the noise pulses formed by the receiver provides a means for determining the noise modulation bandwidth of a noise jammer source.

Abstract: A dual transport channel charge coupled device for coherently processing two analog signals in a bandwidth compression mode of operation, especially for use in a high resolution coherent radar system, is disclosed. An input charge injection stage is included for each transport channel. The input stages are dependently operative to simultaneously inject charge quantities correspondingly representative of concurrent samplings of the two analog signals being processed into their corresponding associated transport channels. Each transport channel comprises N multi-phase controlled stages in an in-line arrangement with the stages of one transport channel respectively corresponding to the stages of the other, the stages being operative to transport the simultaneously injected charge quantities concurrently along their corresponding channels.

Abstract: An impulse generator apparatus for a high resolution Chirp radar utilizing a fast settling time VHF oscillator in combination with a digital counter and a low phase distortion output filter to provide a sharp gated sinusoid impulse waveform to excite the receiver dispersive delay line.

Abstract: Noise induced hunting is eliminated in successive ranged digital/analog converter bias correction circuits by means of a digital hysteresis circuit. The digital hysteresis circuit comprehends a first up/down counter that counts to its extremums from a pre-set intermediate state in response to enable and up/down input signals. For each extremum count an enable output pulse and a reset pulse is generated at the counter output. The enable output pulses are counted by a second up/down counter the output of which drives a digital/analog converter. Each reset pulse resets the first up/down counter to its pre-set state.

Abstract: An automatic bias adjustment circuit for a successive ranged analog/digital converter (SRADC) that eliminates the need for manual bias adjustments and calibration inputs. The bias correction circuit comprehends dual flip flops that are triggered by selected comparators of the SRADC n bit parallel analog/digital converter. The flip flop output signals control up/down counters whose output bits drive digital/analog converter. The digital/analog converted signals are introduced back into the SRADC analog chain to zero bias errors in a particular sub-range. A disabling circuit prevents operation of the bias adjustment circuits for the first sub-range.

Abstract: An analog-to-digital conversion circuit of the type employing a feedback-type, successive subranging mode of operation is provided. The circuit achieves bipolar input capability using an internal subranging A/C converter which has only a unipolar capability using a single level, unipolar, add-only binary summer to combine successive subranges. The foregoing have been achieved by means of a novel combination of relatively simple circuit elements which have fast settling times.