Abstract: A reconfigurable computing system for accelerating execution of floating point intensive iterative applications. The reconfigurable computing system includes a plurality of interconnected processing elements mounted on a printed circuit board, a host processing system for displaying real-time outputs of the floating point calculations performed by the processing elements, and an interface for connecting the processing elements to the host system. Each of the interconnected processing elements includes a floating point functional unit, operand memory, control memory and a control unit. The floating point functional unit includes a multiply accumulate function. The operand memory includes a plurality of banks of static random access memory. The processing elements are interconnected using a nearest neighbor or hierarchical implementation. The instruction set performed by the floating point functional unit includes arithmetic, control and communication instructions.