Abstract: Overheat and fire detection for aircraft systems includes an optical controller and a fiber optic loop extending from the optical controller. The fiber optic loop extends through one or more zones of the aircraft. An optical signal is transmitted through the fiber optic loop from the optical controller and is also received back at the optical controller. The optical controller analyzes the optical signal to determine the temperature, strain, or both experienced within the zones.

Abstract: The press fitting for a pipe, is provided with a fitting body which has a supporting sleeve with a free end and a pressing sleeve. The pressing sleeve is held substantially concentrically with respect to the supporting sleeve by means of at least one spacer element arranged at the holding end of the pressing sleeve. I the region of the holding end of the pressing sleeve, the fitting body has a locking depression or a locking projection. At the holding end, the cylindrical wall of the pressing sleeve has at least one opening through which a locking element extends to the axial fitting of the pressing sleeve to the fitting body, wherein the locking element projects into the locking depression of the fitting body and ends in the depression, or the locking element engages around or behind the locking projection of the fitting body.

Abstract: A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition.

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

Abstract: A method is proposed for processing a data word, in which the data word comprises a first partial data word and a second partial data word, in which first checkbits are defined for the first partial data word, wherein the first partial data word and the first checkbits form a first codeword, in which second checkbits are defined for the second partial data word, wherein the second partial data word and the second checkbits form a second codeword, in which third checkbits are defined for the data word, wherein at least (i) the data word, (ii) a linking of the first checkbits with the second checkbits, and (iii) the third checkbits are parts of a third codeword.

Abstract: In various embodiments, a method of correcting and/or detecting an error in a memory device is provided. The method may include, in a first operations mode, applying a first code to detect and/or correct an error, and in a second operations mode after an inactive mode and before entering the first operations mode, applying a second code for correcting and/or detecting an error, wherein the first code and the second code have different code words.

Abstract: A circuit having a memory element coupled between and having a full voltage between two supply rails; and a detection unit coupled to the memory element and configured to maintain a substantially constant biasing of the memory element while simultaneously detecting current flow through the memory element.

Abstract: A circuit arrangement for determining a correction signal on the basis of at least one bit error of a binary word is specified, including a plurality of subcircuits (ST), wherein a respective subcircuit is provided for a bit position to be corrected of the binary word, wherein each of the subcircuits provides at least two locator polynomial values, and comprising a selection unit, which determines a correction signal depending on the locator polynomial values and depending on an error signal (err, E). A method for driving such a circuit arrangement is furthermore proposed.

Abstract: A method for data processing is suggested including: (i) transforming electrical variables for each cell of a data bit of a memory into a time domain; and (ii) determining a predetermined state by comparing the transformed electrical variables of at least two data bits.

Abstract: A system and method of refreshing a nonvolatile memory having memory cells. The method includes identifying one or more of the memory cells that do not satisfy a data retention test; remapping the one or more identified memory cells from original memory addresses to spare memory addresses; and refreshing the identified memory cells.

Abstract: An apparatus includes a processing unit and a memory. The processing unit is configured to encode a plurality of bits to obtain a plurality of encoded bits, the processing unit is configured to determine an inversion decision. When the inversion decision indicates that the subset of the encoded bits shall not be inverted, the processing unit is configured to store, as a stored word, bits of the first codeword into the memory. When the inversion decision indicates that the subset of the encoded bits shall be inverted, the processing unit is configured to invert each encoded bit of a subset of the encoded bits to obtain a second codeword and to store the second codeword into the memory.

Abstract: A memory device includes a memory with first memory cells and second memory cells, which are different from the first memory cells. In the first memory cells there is stored a first bit sequence and in the second memory cells there is stored a second bit sequence. The memory device includes a memory controller, which is configured to check the first bit sequence with a frequency (×1/T) assigned to the first memory cells. The frequency (×1/T) assigned to the first memory cells depends on an item of reliability information for the first memory cells. The memory controller is configured in the case of an error state to correct an erroneous bit of the first bit sequence and to write back at least the corrected bit into the memory. The second bit sequence is checked less often than the first bit sequence on the basis of an item of reliability information for the second memory cells.

Abstract: A method is proposed for storing bits in memory cells of a memory, wherein in two successive write operations first and second wits are written to identical memory cells at an identical address, without the memory cells being erased after the first write operation, wherein first check bits are stored in further first memory cells and second check bits are stored in further second memory cells. A corresponding device is furthermore specified.

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract: Systems, apparatuses, and methods of and for an ophthalmic illuminated infusion line are provided. An example ophthalmic illuminated infusion line may include an infusion arrangement having a first flexible elongate member and a flow tube. The first flexible elongate member may have a lumen configured to deliver a fluid to an eye of a patient during a surgical procedure. The flow tube may be sized to penetrate the eye of the patient and deliver the fluid to an interior of an eye to maintain intraocular pressure during a surgical procedure. The ophthalmic illuminated infusion line may also include an optical fiber coupled to the infusion arrangement and configured to penetrate the eye of the patient with the flow tube and transmit light to illuminate the interior of the eye during the surgical procedure at the same time that the flow tube delivers the fluid to the interior of the eye.

Abstract: An illuminated microsurgical instrument is provided herein that includes a microsurgical instrument having a tubular member arranged to treat patient tissue at a surgical site, the tubular member having a distal tip, an inner surface, and an outer surface. The inner surface defines a lumen. The outer surface has a notch formed therein. The illuminated microsurgical instrument further includes an optical fiber arranged to deliver light to the surgical site. The optical fiber includes a proximal end arranged to receive a light beam from a light source and also includes a curved distal end arranged to emit light adjacent to the distal tip. A portion of the curved distal end is positioned within the notch and curves away from the tubular member.

Abstract: Some embodiments of the present disclosure relate to improved regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.

Abstract: An optical apparatus includes a housing, a deformable lens, and a lens shaper. The lens shaper defines the shape of the deformable lens. A first mechanism is positioned within the housing to adjust an optical property of the deformable lens. A second mechanism is positioned within the housing to adjust an optical property of the deformable lens. The second mechanism is at least one of an electromechanical actuator or motor. The first mechanism and the second mechanism are different types of mechanisms.

Abstract: A method and associated apparatus to determine a reference value on the basis of a plurality of half reference values stored in memory cells is disclosed, wherein the plurality of half reference values are read from the memory cells, wherein a subset of half reference values is determined from the plurality of half reference values, and wherein the reference value is determined on the basis of the subset of half reference values.

Abstract: A memory circuit including a memory cell configured to provide a charge, voltage, or current to an associated bit-line; a sense amplifier configured to sense the charge, voltage, or current on the bit-line; a word-line circuit configured to control a word-line of the memory cell; and a tracking circuit configured to track one or more conditions of the memory circuit and provide a timing control signal at an output operative to adaptively control the word-line circuit.