Abstract: A BIST controller (112) and methodology uses the DRAM controller (108) refresh signals to test the data retention characteristics of a DRAM memory array (132). The BIST controller blocks a fraction of the refresh cycles generated by the DRAM controller to provide a margin of confidence above the DRAM's specified retention time. The BIST controller is especially suited to embedded applications in which access to the memory is indirect and to applications in which the memory system is modular. The invention may also be used to characterize the actual retention time of a particular DRAM allowing the system to optimize the DRAM's refresh interval.

Abstract: A method and system for performing memory repair via redundant rows of memory uses memory elements (208 and 210) for redundant row selection instead of conventional fuses. An on-chip test controller (110) is capable of testing memory rows (106) either at wafer probe, at final testing after manufacturing, or after memory chip packaging and/or final sale to end users. If this testing identifies faulty memory rows in the memory array at any time, the electrically programmable memory elements (208 and 210) can be internally re-programmed to create a new memory configuration which includes redundant memory rows (108). This new memory configuration is enabled in order to remove the newly-detected and previously-detected faulty memory rows from active memory in the memory array.

Abstract: A method and apparatus for allowing an integrated circuit to be hard-wired into one of a plurality of modes of operation by providing a plurality of mode bonding pads (104-108). Based upon customer demand, a reset post (102) or like external terminal of the integrated circuit is wire bonded or conductively coupled to only one of the plurality of mode pads (104-108). By bonding only one of the mode pads (104-108) to the reset pin, one of the plurality of distinct modes of operation is enabled upon reset.