Abstract: A programmable integrated circuit device includes a programmable core, a boot device configured to boot up the programmable core, and a one-time programmable memory module controlling life cycle states of the programmable integrated circuit device, including (i) an operational state during which programming resources of the programmable device are locked, and (ii) an inspection state in which the programming resources of the programmable device are accessible. The one-time programmable memory module is configured to allow unidirectional advance from the operational state to the inspection state, when authorized by a lock control circuit responsive to control signals from the boot device to authorize the unidirectional advance from the operational state to the inspection state. Authorization of the unidirectional advance may be limited to a time interval during a boot cycle of the programmable device. The unidirectional advance may be based on receipt of an authenticated request from a requester.

Abstract: A programmable integrated circuit device includes a programmable core, a boot device configured to boot up the programmable core, and a one-time programmable memory module controlling life cycle states of the programmable integrated circuit device, including (i) an operational state during which programming resources of the programmable device are locked, and (ii) an inspection state in which the programming resources of the programmable device are accessible. The one-time programmable memory module is configured to allow unidirectional advance from the operational state to the inspection state, when authorized by a lock control circuit responsive to control signals from the boot device to authorize the unidirectional advance from the operational state to the inspection state. Authorization of the unidirectional advance may be limited to a time interval during a boot cycle of the programmable device. The unidirectional advance may be based on receipt of an authenticated request from a requester.

Abstract: A network device including access and test ports, an interface, and first and second controllers. The interface receives an Ethernet frame transmitted over an Ethernet network to the network device. The Ethernet frame includes bits for testing or debugging the memory-mapped device and is received at the interface based on an output of a host device. The first controller converts the Ethernet frame to a first access frame. The test port receives a diagnostic signal transmitted from the host device to the network device. The second controller converts the diagnostic signal to a second access frame and controls passage of the access frames to the memory-mapped device via the access port. The first controller tests or debugs the memory-mapped device based on data received from a register of the memory-mapped device. The data is written in the register based on the first and second access frames.

Abstract: A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

Abstract: A network device including access and test ports, an interface, and first and second controllers. The interface receives an Ethernet frame transmitted over an Ethernet network to the network device. The Ethernet frame includes bits for testing or debugging the memory-mapped device and is received at the interface based on an output of a host device. The first controller converts the Ethernet frame to a first access frame. The test port receives a diagnostic signal transmitted from the host device to the network device. The second controller converts the diagnostic signal to a second access frame and controls passage of the access frames to the memory-mapped device via the access port. The first controller tests or debugs the memory-mapped device based on data received from a register of the memory-mapped device. The data is written in the register based on the first and second access frames.

Abstract: A network device is provided and operative to secure remote access to an internal component including a processor and/or a register. The network device includes an Ethernet interface, an access port, and a controller. The Ethernet interface receives, from a host device, frames transmitted over an Ethernet network. The access port is physically connected to the internal component and physically inaccessible to the host device. The controller is physically connected to the access port. The controller: accesses the internal component via the access port; based on the frames, determines whether the host device is authorized; if the host device is not authorized, prevent the host device from accessing the processor or the register; and if the host device is authorized, permit the host device, via the Ethernet interface and the access port, to control operation of the processor or change the contents of the register.

Abstract: A packet generator includes a checksum calculator configured to distinguish, in a communication packet belonging to a sequence of packets, between (i) one or more constant values of a header of the packet, the one or more constant values remaining unchanged across the packets in the sequence, (ii) a payload of the packet, and (iii) one or more variable values of the header, the one or more variable values changing among the packets in the sequence, to determine a constant-values partial checksum calculated over the constant values of the header, to calculate a payload partial checksum over the payload, to calculate a final checksum value for the packet based on (i) the constant-values partial checksum, (ii) the payload partial checksum and (iii) the variable values of the header, and to insert the final checksum value into the packet. An egress interface transmits the packet over a network.

Abstract: A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

Abstract: A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

Abstract: A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

Abstract: A packet generator includes a checksum calculator configured to distinguish, in a communication packet belonging to a sequence of packets, between (i) one or more constant values of a header of the packet, the one or more constant values remaining unchanged across the packets in the sequence, (ii) a payload of the packet, and (iii) one or more variable values of the header, the one or more variable values changing among the packets in the sequence, to determine a constant-values partial checksum calculated over the constant values of the header, to calculate a payload partial checksum over the payload, to calculate a final checksum value for the packet based on (i) the constant-values partial checksum, (ii) the payload partial checksum and (iii) the variable values of the header, and to insert the final checksum value into the packet. An egress interface transmits the packet over a network.

Abstract: A network device is provided and operative to secure remote access to an internal component including a processor and/or a register. The network device includes an Ethernet interface, an access port, and a controller. The Ethernet interface receives, from a host device, frames transmitted over an Ethernet network. The access port is physically connected to the internal component and physically inaccessible to the host device. The controller is physically connected to the access port. The controller: accesses the internal component via the access port; based on the frames, determines whether the host device is authorized; if the host device is not authorized, prevent the host device from accessing the processor or the register; and if the host device is authorized, permit the host device, via the Ethernet interface and the access port, to control operation of the processor or change the contents of the register.

Abstract: A chipset including one or more system-on-chips. The chipset includes a memory-mapped device, an Ethernet interface, and a remote management controller. The memory-mapped device includes a test access port and is configured to access a register based on an address of a memory corresponding to the register. The Ethernet interface is configured to receive Ethernet frames transmitted over an Ethernet network. One or more of the Ethernet frames are received from a host device. The one or more of the Ethernet frames are received to test the one or more system-on-chips. The remote management controller is coupled to the test access port. The remote management controller is configured to, based on the one or more of the Ethernet frames, remotely control operation of the memory-mapped device or another device in the one or more system-on-chips, and restrict (a) testing of the one or more system-on-chips or the memory-mapped device, and (b) access by the host device to the register.

Abstract: Systems, methods, and other embodiments associated with ordering packets into a transmission order within a queue are described. According to one embodiment, an apparatus includes shaper logic configured to (i) respectively determine launch times for packets received from a host bus, and (ii) order the packets into a transmission order according to the launch times. The launch times are expected transmission times for the packets that are provided according to one or more attributes associated with each respective one of the packets. The apparatus includes a queue configured to store the packets in the transmission order for transmission onto a network in a single stream. The shaper logic is configured to merge the packets from multiple streams into the transmission order when providing the packets to the queue.

Abstract: A chipset including one or more system-on-chips. The chipset includes a memory-mapped device, an Ethernet interface, and a remote management controller. The memory-mapped device includes a test access port and is configured to access a register based on an address of a memory corresponding to the register. The Ethernet interface is configured to receive Ethernet frames transmitted over an Ethernet network. One or more of the Ethernet frames are received from a host device. The one or more of the Ethernet frames are received to test the one or more system-on-chips. The remote management controller is coupled to the test access port. The remote management controller is configured to, based on the one or more of the Ethernet frames, remotely control operation of the memory-mapped device or another device in the one or more system-on-chips, and restrict (a) testing of the one or more system-on-chips or the memory-mapped device, and (b) access by the host device to the register.

Abstract: The present disclosure describes techniques and apparatuses for arbitration of time-sensitive data transmissions. In some aspects a start of the first scheduled data transmission may be advanced effective to increase the duration of time between an end of the first scheduled data transmission and a start of a second scheduled data transmission. A non-scheduled data transmission can then be performed during the increased duration of time between the end of the advanced first scheduled data transmission and the start of the second scheduled data transmission.