Abstract: An electrostatic discharge (ESD) protection circuit including a first isolation structure on a first path, a second isolation structure on a second path, and a discharging element such as a Harrington diode structure connected to the first and second isolation structures. The isolation structures may comprise resistive elements. The ESD protection circuit is adaptable for use with microcircuits positioned in portable data carriers.

Abstract: A histogram generator system uses a sensor to periodically sample a value of a physical variable to produce at least one sample of the physical variable and a selector allocate each sample of the value of the physical variable into a corresponding counter of a counter array. The counter accumulates a number of occurrences of the value of the sample(s) of the physical variables.

Abstract: A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which has the lowest breakdown voltage for a given technology is incorporated into the SCR enabling a SCR trigger voltage determined by the lowest breakdown-structure.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor (10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: A programmable device (10) is formed from a silicided MOS transistor. The transistor 10) is formed at a face of a semiconductor layer (12), and includes a diffused drain region (17, 22) and a source region (19, 24) that are spaced apart by a channel region (26). At least the drain region (22) has a surface with a silicided layer (28) formed on a portion thereof. The application of a programming voltage in the range of ten to fifteen volts from the drain region (17, 22) to the source region (19, 24) has been discovered to reliably form a melt filament (40) across the channel region (26). A gate voltage (V.sub.g) may be applied to the insulated gate (14) over the channel region (26) such that a ten-volt programming voltage (V.sub.PROG) will cause melt filaments to form in those transistors to which the gate voltage is applied, but will not cause melt filaments to form in the remaining transistors (10) of an array.

Abstract: Methods of doping Hg.sub.1-x Cd.sub.x Te (50) with fast diffusing dopants by immersion in a mercury reservoir (32) doped with the desired dopants are disclosed. Also, methods of core annihilation of Hg.sub.1-x Cd.sub.x Te slices or ingots by immersion in a heated mercury reservoir are disclosed. Preferred embodiments include dopants such as copper in a mercury reservoir (32) that is heated to 270.degree. C. for a Hg.sub.1-x Cd.sub.x Te slice, and a reservoir (32) that is heated to 150.degree. C. for a thin film of Hg.sub.1-x Cd.sub.xn Te on a CdTe substrate.