Abstract: An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Abstract: A clock distribution and control system (10) includes one counter (30) in a clock generation domain and another counter (40) in a phase-delayed clock domain. The phase-delayed domain counter (40) output is combined with a programmable offset value chosen based on the phase delay of the clock distribution system. The result is used to insure that communication between logic in the clock generation clock domain and logic in the phase-delayed clock domain occurs deterministically on the correct clock edge for a range of clock frequencies.

Abstract: The disclosed data processor (10) has a future file (60) for providing the most recent value of a set of architectural registers (32, 36) to the various execution units (20, 22, 24, 26, 28, 30) of the data processor. The most recent value of the set of architectural registers is determined with respect to the original instruction sequence. The future file provides a single source for operand look-up at instruction dispatch and can be corrected in a single cycle in the event of an exception condition.