Abstract: A circuit for fast interrupt handling is disclosed. An apparatus includes a processor circuit having an execution pipeline and a table configured to store a plurality of pointers that correspond to interrupt routines stored in a memory circuit. The apparatus further includes an interrupt redirect circuit configured to receive a plurality of interrupt requests. The interrupt redirect circuit may select a first interrupt request among a plurality of interrupt requests of a first type. The interrupt redirect circuit retrieves a pointer from the table using information associated with the request. Using the pointer, the execution pipeline retrieves first program instruction from the memory circuit to execute a particular interrupt routine.

Abstract: A circuit for fast interrupt handling is disclosed. An apparatus includes a processor circuit having an execution pipeline and a table configured to store a plurality of pointers that correspond to interrupt routines stored in a memory circuit. The apparatus further includes an interrupt redirect circuit configured to receive a plurality of interrupt requests. The interrupt redirect circuit may select a first interrupt request among a plurality of interrupt requests of a first type. The interrupt redirect circuit retrieves a pointer from the table using information associated with the request. Using the pointer, the execution pipeline retrieves first program instruction from the memory circuit to execute a particular interrupt routine.

Abstract: Methods and apparatuses are presented for reducing the power consumed in an in-line memory module. In some embodiments, the method may include monitoring a memory requirement of a computer system, the computer system comprising a plurality of memory modules. In the event that the memory requirement changes, unmapping at least one of the plurality of memory modules and maintaining a low power state for the at least one unmapped memory module. The method may further comprise selectively re-initializing the plurality of memory modules such that the at least one unmapped memory module remains in a low power state while the remainder of the plurality of memory modules are in a non-low power state. Where, in the event that the memory requirement changes again, the method also may comprise re-programming the memory controller with an identifier associated with the at least one unmapped memory module.

Abstract: A method and apparatus colors the conventional error codes of each word of a multiword transmission to facilitate the detection of words which are out of order or not part of the transmission, without affecting the data in the word. A 1-bit by n-bit matrix is assembled using the header word, and zeros for the header of the multiword transmission, or the data word, error code, if any, an identifier portion of the header word and zeros for each data word, and the 1-bit by n-bit matrix is multiplied by an n-bit by m-bit matrix assembled from a conventional error coding matrix and other matrices. The result either produces an error code to be sent with the header or data, or a check code to be verified as all zeros to indicate the absence of bit errors within the header or data word, and that the word is in the proper packet and in the proper sequence within the packet.

Abstract: Arbitration apparatus and method coordinate access to an output of a routing device in a packet switching network. Access to the output is granted to requests having the highest priority in a current arbitration cycle. For requests having the same priority, access is granted to the first of such requests received. Before granting a request, the arbitration apparatus ensures a receiving input buffer has sufficient space for a data packet, as well as any higher priority traffic.