Abstract: A method for acquiring a 3D image of a sample structure includes acquiring a first raw 2D set of 2D images of a sample structure at a limited number of raw sample planes; calculating a 3D image of the sample structure represented by a 3D volumetric image data set; and extracting a measurement parameter from the 3D volumetric image data set. A further number of interleaving 2D image acquisitions are recorded at a further number of interleaved sample planes which do not coincide with previous acquisition sample planes. The steps “calculating,” “extracting” and “assigning” are repeated for the further interleaving 2D set until convergence or a maximum number of 2D image acquisitions is recorded. A projection system used for such method comprises a projection light source, a rotatable sample structure holder and a spatially resolving detector. Such method can also be used to acquire virtual tomographic images of a sample.

Abstract: A detection system serves for X-ray inspection of an object. An imaging optical arrangement serves to image the object in an object plane illuminated by X-rays generated by an X-ray source. The imaging optical arrangement comprises an imaging optics to image a transfer field in a field plane into a detection field in a detection plane. A detection array is arranged at the detection field. An object mount holds the object to be imaged and is movable relative to the X-ray source via an object displacement drive along at least one lateral object displacement direction in the object plane. A shield stop with a transmissive shield stop aperture is arranged in an arrangement plane in a light path and is movable via a shield stop displacement drive in the arrangement plane.

Abstract: In a method to acquire a 3D image of a sample structure initially a first raw 2D set of 2D images of a sample structure is acquired at a limited number of raw sample planes. From this first raw 2D set a 3D image of the sample structure being represented by a 3D volumetric image data set is calculated and a measurement parameter is extracted from the 3D volumetric image data set. Such measurement parameter is assigned to the number of 2D image acquisitions recorded during the acquisition step. Then, a further interleaving 2D set of 2D images of the sample structure is required by recording a further number of interleaving 2D image acquisitions at a further number of interleaved sample planes which do not coincide with the previous acquisition sample planes. The steps “calculating,” “extracting” and “assigning” are repeated for the further interleaving 2D set. The actual and the last extracted measurement parameters are compared to check whether a convergence criterion is met.

Abstract: A detection system serves for X-ray inspection of an object. An imaging optical arrangement serves to image the object in an object plane illuminated by X-rays generated by an X-ray source. The imaging optical arrangement comprises an imaging optics to image a transfer field in a field plane into a detection field in a detection plane. A detection array is arranged at the detection field. An object mount holds the object to be imaged and is movable relative to the light source via an object displacement drive along at least one lateral object displacement direction in the object plane. A shield stop with a transmissive shield stop aperture is arranged in an arrangement plane in a light path and is movable via a shield stop displacement drive in the arrangement plane.

Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.

Abstract: A flip chip package includes a substrate having a die attach surface, and a die mounted on the die attach surface with an active surface of the die facing the substrate. The die includes a base, a passivation layer overlying the base, a topmost metal layer overlying the passivation, and a stress buffering layer overlying the topmost metal layer, wherein at least two openings are disposed in the stress buffering layer to expose portions of the topmost metal layer. The die is interconnected to the substrate through a plurality of conductive pillar bumps on the active surface. At least one of the conductive pillar bumps is electrically connected to one of the exposed portions of the topmost metal layer through one of the at least two openings.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

Abstract: An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer is formed such a portion of the solder resist layer and a portion of the first conductive trace collectively have a T-shaped cross section.

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, an underfill material is provided that fills a gap between the substrate and the semiconductor die.

Abstract: A flip chip package includes: a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein part of the copper column overhangs the via opening.

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract: A method for fabricating a molded interposer package includes performing a first anisotropic etching process to remove a portion of the metal sheet from a top surface of the metal sheet, thereby forming a plurality of first recesses in the metal sheet, forming a molding material covering the top surface, filling the first recesses, forming a plurality of first via openings in the molding material, wherein the first via openings expose the top surface, forming a plurality of first metal vias in the first via openings and a plurality of first redistribution layer patterns respectively on the first metal vias, performing a second anisotropic etching process to remove a portion of the metal sheet from a bottom surface of the metal sheet until a bottom of the molding material is exposed, and forming a solder mask layer on the molding material, leaving the first redistribution layer patterns exposed.

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.