Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system are disclosed. A memory controller may be connected to a memory bank inserted into a memory bank insertion area, via an interconnect line such as row address strobe (RAS) signal line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks, type detection operations may be performed on the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.