Abstract: The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity.

Abstract: Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

Abstract: A shared time-of-day (TOD) clock modification bit is used in a multiprocessing system in which the timing facilities in two or more CPUs are implemented as a function of a single TOD clock. This bit helps avoid timer errors that occur as the result of one central processing unit (CPU) changing the TOD clock value while another CPU is executing an instruction which determines a CPU timer value. Whenever the microcode in any one of the CPUs reads the TOD clock, it obtains the Shared TOD Clock Modification Bit in addition to the TOD value. This bit indicates if the TOD clock read operation just completed is the first such operation executed by that CPU since the TOD clock was updated by another CPU sharing the same TOD clock. If it is, certain instructions take action to correct timer errors introduced by the change in the TOD clock value.