Patents by Inventor Thomas Obkircher
Thomas Obkircher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8417836Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.Type: GrantFiled: March 5, 2012Date of Patent: April 9, 2013Assignee: Skyworks Solutions, Inc.Inventor: Thomas Obkircher
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Patent number: 8374300Abstract: A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.Type: GrantFiled: March 22, 2012Date of Patent: February 12, 2013Assignee: Intel CorporationInventors: Jaleh Komalil, Thomas Obkircher, William J. Domino
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Patent number: 8374297Abstract: A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.Type: GrantFiled: September 15, 2008Date of Patent: February 12, 2013Assignee: Intel CorporationInventors: Jaleh Komaili, Thomas Obkircher, William J. Domino
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Publication number: 20120319747Abstract: Apparatus and methods for detecting a lock in a phase-locked loop (PLL) are disclosed. In one aspect, a lock detect component includes a reference multiplier and a lock detect. The reference multiplier can receive a reference signal, a divider signal, and a voltage-controlled oscillator (VCO) output generated by a VCO in a PLL from which the divider signal is generated. The reference multiplier can also generate a multiplied reference signal using the reference signal and the VCO output. The multiplied reference signal can have a frequency that is an integer multiple of a frequency of the reference signal. The lock detect can detect a phase lock of the reference signal and the divider signal based at least in part on comparing a signal generated from a delayed reference signal and a signal generated from a delayed divider signal for a predetermined period of time.Type: ApplicationFiled: June 20, 2011Publication date: December 20, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Ardeshir Namdar-Mehdiabadi, Yong Hee Lee, Thomas Obkircher
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Publication number: 20120280730Abstract: Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations.Type: ApplicationFiled: May 3, 2011Publication date: November 8, 2012Applicant: Skyworks Solutions, Inc.Inventors: Thomas Obkircher, Bipul Agarwal, Wei-Hong Chen
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Publication number: 20120242379Abstract: Apparatus and methods for distributing spurious tones through the frequency domain are disclosed. One such apparatus can include a dithering circuit configured to generate a sequence of numbers that exhibit statistical randomness and a variable frequency circuit configured to adjust a frequency of an output based on the sequence of numbers so as to spread energy of spurious tones in a frequency response of the output to lower a noise floor. In one example, spurious tones can be reduced in a negative voltage generator of a radio frequency (RF) attenuator.Type: ApplicationFiled: March 22, 2012Publication date: September 27, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Thomas Obkircher, William J. Domino, Bipul Agarwal
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Publication number: 20120183106Abstract: A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.Type: ApplicationFiled: March 22, 2012Publication date: July 19, 2012Inventors: Jaleh Komaili, Thomas Obkircher, William J. Domino
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Patent number: 8212593Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.Type: GrantFiled: June 3, 2011Date of Patent: July 3, 2012Assignee: Skyworks Solutions, Inc.Inventor: Thomas Obkircher
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Publication number: 20120166677Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.Type: ApplicationFiled: March 5, 2012Publication date: June 28, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Thomas Obkircher
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Publication number: 20120134402Abstract: A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.Type: ApplicationFiled: January 30, 2012Publication date: May 31, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Jaleh Komaili, John E. Vasa, Thomas Obkircher
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Publication number: 20120079138Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.Type: ApplicationFiled: September 27, 2010Publication date: March 29, 2012Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Thomas Obkircher
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Patent number: 8135881Abstract: A serial peripheral interface (SPI) controller can be configured in response to data received via the interface. The SPI controller can perform read and write operations upon registers of a register bank in response to signals received via one or more of a data signal line, a clock signal line, and a select signal line. By detecting combinations of signals on one or more of the data signal line, clock signal line and select signal line, the SPI controller can detect the initiation of data read and write operations that may be in accordance with any of several different SPI protocols.Type: GrantFiled: September 27, 2010Date of Patent: March 13, 2012Assignee: Skyworks Solutions, Inc.Inventor: Thomas Obkircher
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Patent number: 8126094Abstract: A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.Type: GrantFiled: January 7, 2009Date of Patent: February 28, 2012Assignee: Skyworks Solutions, Inc.Inventors: Jaleh Komaili, John E. Vasa, Thomas Obkircher
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Publication number: 20110298503Abstract: A method and apparatus is disclosed for voltage-controlled oscillator selection in a multi-mode system having multiple voltage-controlled oscillators. Part of oscillator selection is a calibration operation that utilizes maximum and minimum capacitance limits for a voltage-controlled oscillator, which translates to a frequency range, to calculate overlap regions. Overlap regions comprise frequency ranges that overlap such that the overlap region may be generated by two voltage-controlled oscillators with adjacent frequency ranges. One voltage-controlled oscillator selection routine comprises a real time voltage-controlled oscillator calibration and selection routine that executes every time the system requests a new frequency. Another selection routine comprises a start-up routine that executes only at power up or periodically.Type: ApplicationFiled: June 2, 2010Publication date: December 8, 2011Inventors: Thomas Obkircher, Bipul Agarwal, Georgi Taskov
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Publication number: 20110235772Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.Type: ApplicationFiled: June 3, 2011Publication date: September 29, 2011Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Thomas Obkircher
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Patent number: 7956656Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.Type: GrantFiled: March 4, 2010Date of Patent: June 7, 2011Assignee: Skyworks Solutions, Inc.Inventor: Thomas Obkircher
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Patent number: 7919997Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.Type: GrantFiled: May 8, 2008Date of Patent: April 5, 2011Assignee: Skyworks Solutions, Inc.Inventor: Thomas Obkircher
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Publication number: 20100172450Abstract: A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.Type: ApplicationFiled: January 7, 2009Publication date: July 8, 2010Applicant: Skyworks Solutions, Inc.Inventors: Jaleh Komaili, John E. Vasa, Thomas Obkircher
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Publication number: 20100156476Abstract: Systems and methods for providing a clock signal are provided. A frequency multiplier circuit is provided that can include a plurality of serially connected delay elements that are configured to generate a plurality of delay tap signals from an input signal. The frequency multiplier circuit can also include a phase detector configured to receive a first selected delay tap signal and the input signal. The phase detector can detect a phase shift between the first selected delay tap signal and the input signal, and can generate a phase detection signal indicative of a value of the phase shift. The frequency multiplier circuit can also include a digital logic gate configured to receive the input signal and a second selected delay tap signal. The digital logic gate can be further configured to generate an output signal responsive to the second selected delay tap signal and the input signal. The frequency multiplier circuit can also include a controller coupled to the phase detector and coupled to an output gate.Type: ApplicationFiled: March 4, 2010Publication date: June 24, 2010Applicant: SKYWORKS SOLUTIONS, INC.Inventor: Thomas Obkircher
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Publication number: 20100067622Abstract: A controller and a circuit work together to enable a selective and dynamic adjustment to correct phase and gain imbalances in quadrature signal paths of a receiver. Under select conditions, it has been determined that statistical estimates of gain and phase imbalance can be applied to adjust signals in the quadrature signal paths of a receiver. The controller validates the select conditions before updating the estimate of the gain imbalance and the estimate of the phase imbalance. The controller directs a compensator under select operating conditions such that validated dynamic estimates of the gain and phase imbalance or calibration data is applied to the quadrature signal paths. The controller disables the compensator and enables an estimator and a calculator when estimates are unavailable for the present operating conditions.Type: ApplicationFiled: September 15, 2008Publication date: March 18, 2010Applicant: Skyworks Solutions, Inc.Inventors: Jaleh Komaili, Thomas Obkircher, William J. Domino