Abstract: Technologies are disclosed for detection and display of an indication of a gingivitis condition and/or a periodontal pocket assessment of a subject's oral cavity via a digital representation of the oral cavity. Using scan data of the oral cavity, one or more teeth in the oral cavity may be indicated. A first assessment location proximate to a first tooth of the one or more teeth may be indicated. A first image may be generated that may include the first assessment location and one or more first data channels. The one or more first data channels may comprise color data and topological information corresponding to the first assessment location. Using one or more machine-learning algorithms, a modified gingival index (MGI) value and/or a periodontal pocket depth assessment may be determined and displayed for the first assessment location based on the first image and the one or more first data channels.

Abstract: A variable length headless compression screw insertion system includes a compression screw and a driver assembly for driving the compression screw into a bone. The compression screw has a bone screw and a compression sleeve coupled to the bone screw. The bone screw includes a proximal end having an external threading threadably received in the compression sleeve, and the compression sleeve includes a proximal end having a predefined drive feature and an external threading. The driver assembly includes a sleeve coupler adapted to threadably receive the external threading of the compression sleeve. A ram driver is coupled to the sleeve coupler and has a predetermined length such that its distal end is shaped to contact the proximal end of the bone screw to prevent translation of the bone screw relative to the compression sleeve.

Abstract: Providing memory prefetch instructions with completion notifications in processor-based devices is disclosed. In this regard, an instruction set architecture (ISA) of a processor-based device provides a memory prefetch instruction that, when executed by a processor of a processor-based device, causes the processor to perform a memory prefetch operation by asynchronously retrieving a memory block from the system memory based on the memory address, and storing the memory block in a cache memory of the processor-based device. In response to completing the memory prefetch operation, the processor then notifies an executing software process that the memory prefetch operation is complete. Based on the notification, the executing software process may ensure that any subsequent memory access requests are not attempted until the memory prefetch operation is complete.

Abstract: Systems and methods for adjusting resistance on an exercise apparatus include a first resistance apparatus having an adjusting bracket, magnetic members mounted on an inner surface of the adjusting bracket, a stepper motor having an adjusting shaft and operable to traverse a portion of the length of the adjusting shaft. At a first position, the magnetic members are disposed above a flywheel, and in a second position, the magnetic members are disposed on opposite sides of the flywheel, providing resistance thereto. A load cell couples the adjusting bracket to the frame and generates a signal corresponding to the movement of the adjusting bracket. A computing system calculates resistance, rpms, power from load cell signal, stepper motor position, shaft rotational position and other sensor inputs.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations, set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions is disclosed. The processor is configured to support execution of read and/or write instructions that include obsolescence encoding indicating that one or more of its source and/or target register operands are to be obsoleted by the processor. A register encoded as obsolescent means the data value stored in such register will not be used by subsequent instructions in an instruction stream, and thus does not need to be retained. Thus, such register can be set as being in an obsolescent state so that the data value stored in such register can be ignored to improve performance. As one example, data values for registers having an obsolescent state can be ignored and thus not stored in a saved context for a process being switched out, thus conserving memory and improving processing time for a process switch.

Abstract: Process dedicated in-memory translation lookaside buffers (TLBs) (mTLBs) for augmenting a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PA) in a processor-based system is disclosed. In disclosed examples, a dedicated in-memory TLB is supported in system memory for each process so that one process's cached page table entries do not displace another process's cached page table entries. When a process is scheduled to execute in a central processing unit (CPU), the in-memory TLB address stored for such process can be used by page table walker circuit in the CPU MMU to access the dedicated in-memory TLB for executing the process to perform VA to PA translations in the event of a TLB miss to the MMU TLB. If a TLB miss occurs to the in-memory TLB, the page table walker circuit can walk the page table in the MMU.

Abstract: Systems and methods for adjusting resistance on an exercise apparatus include a first resistance apparatus having an adjusting bracket, magnetic members mounted on an inner surface of the adjusting bracket, a stepper motor having an adjusting shaft and operable to traverse a portion of the length of the adjusting shaft. At a first position, the magnetic members are disposed above a flywheel, and in a second position, the magnetic members are disposed on opposite sides of the flywheel, providing resistance thereto. A load cell couples the adjusting bracket to the frame and generates a signal corresponding to the movement of the adjusting bracket. A computing system calculates resistance, rpms, power from load cell signal, stepper motor position, shaft rotational position and other sensor inputs.

Abstract: A method, apparatus, and system for storing memory encryption realm key IDs is disclosed. A method comprises accessing a memory ownership table with a physical address to determine a realm ID associated with the physical address, accessing a key ID association structure with the realm ID to determine a realm key IS associated with the realm ID, and initiating a memory transaction based on the realm key ID. Once retrieved, the realm key ID may be stored in a translation lookaside buffer.

Abstract: Performing speculative address translation in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that defines a speculative translation instruction such as an enqueue instruction for offloading operations to a peripheral device. The speculative translation instruction references a plurality of bytes including one or more virtual memory addresses. After receiving the speculative translation instruction, an instruction decode stage of an execution pipeline circuit of the PE transmits a request for address translation of the virtual memory address to a memory management unit (MMU) of the PE. The MMU then performs speculative address translation of the virtual memory address into a corresponding translated memory address.

Abstract: In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

Abstract: Cache-based trace logging using tags in an upper cache level. A processor influxes a cache line into a first cache level from an upper second cache level. Influxing the cache line into the first cache level includes, based on the first cache level being a recording cache, the processor reading a tag that is (i) stored in the second cache level and (ii) associated with the cache line. Based on reading the tag, the processor determines whether a first value of the cache line within the second cache level has been previously captured by a trace. The processor performs one of (i) when the first value is determined to have been previously logged, following a logged value logic path when influxing the cache line; or (ii) when the first value is determined to have not been previously logged, following a non-logged value logic path when influxing the cache line.

Abstract: The hand washing assembly includes a hood defining a cavity within the hood, a valve structure located at least partially within the cavity, and a lever handle. The lever handle is operatively coupled to the valve structure and configured to move the valve structure between a first position in which the valve structure prevents a flow of fluid through the valve structure and a second position in which the valve structure permits the flow of fluid through the valve structure. The lever handle includes a contact surface positioned within the cavity and configured to move toward a top wall of the hood as the valve structure moves into the second position and configured to move away from the top wall as the valve structure moves into the first position.

Abstract: An improved bio-electrochemical wastewater treatment process and system (1) is disclosed. An electrode assembly (4) is defined by interconnecting a set of electrode modules (5). Each electrode module (5) has a first electrode of an anode-cathode pair coated with electrogenic microbes adapted to generate electrons via the consumption of organic matter in wastewater. An electrode module (5) has a second electrode of the anode-cathode pair, and a body, supporting and separating the first and second electrodes. Each electrode module (5) also comprises an interface for physically connecting the module with at least one other of the set.

Abstract: Tracking memory block access frequency in processor-based devices is disclosed herein. In one exemplary embodiment, a processor-based device provides a processing element (PE) that is configured to include an access count table for tracking accesses to memory blocks. The access count table is a packed table that comprises a plurality of access count values, each of which corresponds to a memory block of a plurality of memory blocks. Upon detecting a memory access operation (i.e., data-side operations such as memory load operations, memory store operations, atomic increment operations , set operations, and the like, or instruction-side operations such as code fetch operations) directed to a given memory block, the PE increments an access count value corresponding to the memory block. The access count value then can be accessed (e.g., by a process executing on the PE), and used to determine an access frequency for the memory block.

Abstract: Various aspects disclosed herein relate to combining instructions to load data from or store data in memory while processing instructions in a computer processor. More particularly, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width may be identified in a processor pipeline. In response to determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line, the multiple memory access instructions may be replaced within the processor pipeline with one equivalent memory access instruction that utilizes more of the available bus width than either of the replaced memory access instructions.

Abstract: In some examples, a method comprises determining, at an electronic device having a first component of a first component type, a unique identifier associated with the first component. In some examples, in accordance with a determination that the unique identifier does not match the expected identifier of the component of the first component type in the electronic device, determining that the first component associated with the unique identifier satisfies one or more eligibility criteria. In some examples, in accordance with the determination that the first component associated with the unique identifier satisfies the one or more eligibility criteria, authenticating an association of the first component with the electronic device, including updating an installation counter associated with the first component, and updating the expected identifier for the component of the first type based on the unique identifier of the first component.

Abstract: A log splitter includes a chassis having a support table configured to support a log to be split, a splitter screw having a generally conical shape and mounted to a rotatable screw shaft that is supported by the chassis, and a drive assembly configured to rotate the shaft to impart rotational movement to the splitter screw about a screw axis. The drive assembly includes a motor coupled to the screw shaft via a constant velocity transmission (CVT) (also known as continuously variable transmission). The CVT can provide both high speed and high torque during the splitting process as required to split the log. A fall restriction bar helps restrict a person from accidentally falling onto the splitter screw. An engine-kill bar is pivotally mounted to the chassis. A log-rotation stop mechanism is configured to restrict rotation of a log that gets stuck on the splitter screw.