Abstract: A device is disclosed that includes a first pin to supply power to a first power domain of an integrated circuit, a second pin to supply power to a second power domain of the integrated circuit, a switching regulator and a controller. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and is coupled to the second pin to provide a second regulated power supply to the second power domain. The controller is coupled to the first pin and to the second pin to selectively reduce current flow to at least the second pin during a low power event.

Abstract: A photovoltaic cell includes a photovoltaic layer having a first node and a second node. A first conductive layer is electrically coupled to the second node of the photovoltaic layer so the first conductive layer does not block light from the photovoltaic layer. A second conductive layer is adjacent to but electrically insulated from the first conductive layer, so the second conductive layer is positioned where it does not block light from the photovoltaic layer. At least one through silicon via is electrically coupled to the first node of the photovoltaic layer and the second conductive layer, but is electrically insulated from at least a portion of the photovoltaic layer and the first conductive layer.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A first semiconductor tier has a first tier-to-tier connector for detecting a tier-to-tier coupling in a stacked integrated circuit (IC) device. A second semiconductor tier has a second tier-to-tier connector configured to electrically couple to the first tier-to-tier connector. A tier-to-tier detection circuit electrically couples to the second tier-to-tier connector. The tier-to-tier detection circuit generates an output signal indicative of an electrical coupling between the first semiconductor tier and the second semiconductor tier.

Abstract: An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.

Abstract: An IC device is constructed in a manner that allows for the memory and processor elements to be positioned one above the other on parallel planes of a 3-D structure. Interconnections between the memory(s) and the processor(s) are accomplished by using through substrate stacking (TSS) techniques. This arrangement provides the processor with direct access to the memory by reducing the distance between the memory and the processor.

Abstract: An unassembled stacked IC device includes an unassembled tier. The unassembled stacked IC device also includes a first unpatterned layer on the unassembled tier. The first unpatterned layer protects the unassembled tier from ESD events.

Abstract: The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.

Abstract: A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.

Abstract: A first I/O pad has a first type transistor disposed at a first end of the first I/O pad. A second I/O pad has another first type transistor disposed at a first end of the second I/O pad. The first end of the first I/O pad abuts the first end of the second I/O pad, so the first type transistor is adjacent to the other first type transistor.

Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.

Abstract: A device is disclosed that includes a first pin to supply power to a first power domain of an integrated circuit, a second pin to supply power to a second power domain of the integrated circuit, a switching regulator and a controller. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and is coupled to the second pin to provide a second regulated power supply to the second power domain. The controller is coupled to the first pin and to the second pin to selectively reduce current flow to at least the second pin during a low power event.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: Method and apparatus for performing access censorship in a data processing system (10). In one embodiment, a digital data processing system (10) has a sub-system (34) that can be protected against intrusions, yet is still accessible and/or alterable under certain defined conditions. In a non-volatile storage portion (48) of the data processing system (10), censorship information is stored to enable an access control mechanism. Access control information (42) to selectively disable the access control mechanism is programmably generated. Additional access control information (44) can be employed to reprogram a data processing system (10) containing access protected data in a secure mode.

Abstract: Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

Abstract: A method an apparatus for performing a reset operation in an integrated circuit where a memory programming voltage is recovered allowing use of the memory during reset. The voltage recovery unit includes a high voltage conversion portion active for a first recovery period, and a low voltage conversion portion active for a subsequent second recovery period, the low voltage conversion portion is inactive for the first recovery period. The first and second recovery portions are responsive to assertion of a reset signal and an intermediate reset signal generated before the end of the reset period. Recovery of the programming voltage allows uncorrupted retrieval and use of a configuration word during reset. The high voltage conversion portion includes p-channel devices with robust breakdown resistance, and the low voltage conversion portion includes n-channel devices which provides improved speed of operation.

Abstract: Referring to FIGS. 2, 13, and 14, the tag value transferred by timebase select signals (50) indicates which timebase is presently available on timer bus (71). In one embodiment, each channel (61, 62, 80, 81, and 86) compares the tag value of the timebase select signals (50) with a user programmed tag value stored in a register portion (264). If the stored tag value matches the tag value being driven on the timebase select signals (50), then the match signal (263) is asserted to indicate that the channel is either to provide a timebase value to the timer bus (71) for timebase channels (80, 81), or to receive the timebase value from the timer bus (71) for work and other channels (86). FIG. 15 illustrates examples of how timebase values (namely TB1-TB8) may be selectively provided during the different time slots of a timer bus (e.g. 71).

Abstract: A block erasable flash EEPROM (22) having a single array (68) which can be partitioned into one or more blocks (50-57). The same column decode/block select circuitry (66) is used to provide both column select signals (71) and block select signals (73). The number of blocks (50-57) and the size of each block (50-57) can be determined by the manufacturer during the manufacturing process. Each block (50-57) has a corresponding charge pump (80-87). Each charge pump (80-87) is capable of erasing a single block within the array (68). Each charge pump (80-87) has a variable capacitor (90-97). Each of the variable capacitors (90-97) can be sized according to the size of its corresponding block (50-57).

Abstract: A data processing system (10), comprised of a central processing unit (14) and a memory system (16), has an efficient initialization operation. The memory system (16) provides a bus interface unit (20) to automatically determine whether the system (10) should execute an initialization operation or function in a normal mode of operation. The memory system (16) begins execution of the initialization operation of the system (10) in response to both a logic value of a reset signal and a value of an address transferred by an address bus. The memory system (16) automatically terminates execution of the initialization operation in response to the value of the address transferred by the address bus.

Abstract: A bias voltage generator (12) provides a bias control voltage that is connected to a gate of transistor (32) to sink a predetermined amount of bias current. The bias voltage generator (12) is also connected to a gate of a transistor (31) to limit the voltage to a selected bit-line within an array of flash EEPROM cells (26). The predetermined bias current is summed with the current from a selected flash EEPROM cell (46). A reference current generator portion (22), establishes both a reference current and a reference voltage at a second input to a differential amplifier (35). A current-voltage (I-V) characteristic curve of the reference voltage at the second input of the differential amplifier is approximately symmetrically located between the I-V characteristic curves of a flash EEPROM cell when the logic state of the flash EEPROM cell is in an erased state and a programmed state.