Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A method for dynamically activating a plurality of memory banks by way of a plurality of memory controllers in a chip, each of the memory banks being able to be read and written to independently of the other memory banks and each of the memory banks being able to be activatable by multiple of the plurality of memory controllers in each case. The method includes receiving information about an operating state of the chip, dynamically producing assignments of memory controllers to the memory banks based on the operating state of the chip, and activating the memory banks by way of the memory controllers in accordance with the produced assignments.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n + 1 error syndrome components of a first error code.

Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

Abstract: An approach for correcting at least one byte error in a binary sequence is proposed, the binary sequence comprising a plurality of bytes and being a code word of an error code in the error-free case. The approach comprises the steps of: (i) determining at least one byte error position signal which specifies whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value, based on which an erroneous byte position identified by means of the byte error position signal is correctable, the at least one byte error correction value being determined by virtue of a first value and a second value being determined for each of at least two byte positions based on a coefficient of the locator polynomial, and (iii) correcting the at least one byte error based on the at least one byte error correction value.

Abstract: A solution for detecting a multibyte error in a code word of a shortened error code is proposed, the shortened error code is a ?-byte-correcting error code, wherein bytes of the code word of the shortened error code determined a first range, the non-correctable multibyte error is detected if at least one of the following conditions is met: (a) at least one error position signal does not lie in the first range; (b) at least one error position signal indicates at least one error but fewer than terrors in the first range and no 1-byte error to (??1)-byte error is present.

Abstract: Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s1 of an error syndrome and a second partial error syndrome s2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

Abstract: A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: What is specified is a method for transforming a first binary signal read from a memory, wherein the first binary signal is transformed into a second binary signal provided that the first binary signal is a code word or a predefined code word of a k-out-of-n code, wherein the first binary signal is transformed into a predefined signal provided that the first binary signal is not a code word or is not a predefined code word of the k-out-of-n code, wherein the predefined signal is different than the second binary signal. A corresponding device is furthermore specified.

Abstract: A determination is made that error-correcting code functionality detected a first number of erroneous bits within a memory device. Bits within the memory device are evaluated to identify a subset of the bits as candidate bits. The candidate bits are evaluated to determine whether the error-correcting code functionality returns a non-error state, where no error correction is performed, based upon one or more combinations of candidate bits being inverted. Responsive to the error-correcting code functionality returning the non-error state for only one combination of the one or more combinations of candidate bits being inverted, the one combination of candidate bits is corrected.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

Abstract: In various embodiments, a method of using a memory device is provided. The method may include storing data units, check units of a first code and check units of a second code in memory cells of the memory device, wherein the data units and the check units of the first code form code words of the first code, and wherein the data units and the check units of the second code form code words of the second code, applying the second code for error correction in at least a portion of the data units and/or in at least a portion of the check units of the first code, after the correcting the errors, retaining at least a retaining portion of the data units and of the check units of the first code and deleting at least a deleting portion of the check units of the second code, thereby freeing the memory cells that are occupied by the deleting portion of the check units of the second code, and during a subsequent using of the memory device, storing data in at least a reuse portion of the freed-up memory cells.

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.