Abstract: A method for braking a vehicle, including checking whether a trigger criterion for braking the vehicle is present, and if the trigger criterion is satisfied, causing a conditioning braking pulse through brief pulsed braking such that passengers experience brief braking of the vehicle, and immediately thereafter initiating a braking phase in which the vehicle is braked in at least two partial braking regions by an actual ego deceleration that varies with respect to time, wherein each partial braking region is extended over a partial braking interval and merge into one another without the actual ego deceleration changing abruptly, and the actual ego deceleration in at least one of the partial braking regions is changed continuously over the respective partial braking interval such that a different actual jerk is obtained in each partial braking region, and wherein the actual jerk behaves degressively over at least some partial braking regions.

Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Abstract: An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input.

Abstract: An electrical circuit for driving a bus is described that includes a plurality of branches coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes an over-current validation unit coupled to the transmit data input which is configured to validate an over-current condition detected at a first branch of the plurality of branches based at least in part on the data at the transmit data input. The electrical circuit also includes a branch control unit coupled to the over-current validation unit which is configured to disable at least one of the plurality of branches in response to a validated over-current condition at the first branch.

Abstract: A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

Abstract: A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector.

Abstract: A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

Abstract: The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by t

Abstract: A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

Abstract: A method of transmitting data between different clock domains includes receiving data bits on the basis of a receiving clock, sequentially storing the data bits in a ring buffer, simultaneously transmitting a number of the stored data bits from the ring buffer on the basis of a first transmitting clock, and transmitting the stored data bits from the ring buffer on the basis of a second transmitting clock.

Abstract: The invention provides a data handover unit for transferring data from a first clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a frame of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by

Abstract: A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector.

Abstract: A phase locked loop having reduced inherent noise is provided. The phase locked loop comprises a controlled oscillator for outputting a periodic output signal as a result of a control signal; a feedback unit for providing at least two periodic feedback signals having a constant phase shift to each other and each depending on the output signal; a phase/frequency detector for providing difference signals each depending on a periodic input signal and at least one of the feedback signals; and a control circuit for providing the control signal to the controlled oscillator depending on the difference signals.

Abstract: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core.

Abstract: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core.

Abstract: A memory with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

Abstract: A memory which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.

Abstract: A memory with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.

Abstract: A memory which is capable of reconfiguration between a first mode in which each storage cell is capable of storing a pair of data bits and a second mode in which each storage cell is capable of storing a single data. A memory according to the present teachings includes a storage cell having a first structure and a second structure each capable of a storage state and mechanisms for reconfiguring the memory between a first mode in which the storage states of the first and second structures indicate a first and a second data bit, respectively, and a second mode in which the storage states combine to indicate a data bit.