Abstract: A method for a plurality of pipelines, each having a processing element having first and second inputs and first and second lines, wherein at least one of the pipelines includes first and second logic operable to select a respective line so that data is received at the first and second inputs respectively. A first mode is selected and for the at least one pipeline, the first and second lines of that pipeline are selected such that the processing element of that pipeline receives data via the first and second lines of that pipeline, the first line being capable of supplying data that is different to the second line. A second mode is selected and for the at least one pipeline a line of another pipeline is selected, the second line of the at least one pipeline is selected and the same data at the second line is supplied as the first line.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.

Abstract: A sensor plaster (116) for the transcutaneous measurement of an organ function, more particularly of a kidney function, is proposed. The sensor plaster (116) comprises at least one flexible carrier element (134) having at least one adhesive surface (138) which can be stuck onto a body surface. Furthermore, the sensor plaster (116) comprises at least one radiation source, more particularly a light source (142), wherein the radiation source is designed to irradiate the body surface with at least one interrogation light (162). Furthermore, the sensor plaster (116) comprises at least one detector (146) designed to detect at least one response light (176) incident from the direction of the body surface.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: A function estimation hardware logic unit may be implemented as part of an execution pipeline in a processor. The function estimation hardware logic unit is arranged to calculate, in hardware logic, an improved estimate of a function of an input value, d, where the function is given by 1 ? / ? d i . The hardware logic comprises a plurality of multipliers and adders arranged to implement a mth-order polynomial with coefficients that are rational numbers, where m is not equal to two and in various examples m is not equal to a power of two. In various examples i=1, i=2 or i=3. In various examples m=3.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m?r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m?r?1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m?r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.

Abstract: Apparatus identifies a set of M output memory addresses from a larger set of N input memory addresses containing at least one non-unique memory address. A comparator block performs comparisons of memory addresses from a set of N input memory addresses to generate a binary classification dataset that identifies a subset of addresses from the set of input addresses, where each address in the subset identified by the binary classification dataset is unique within that subset. Combination logic units receive a predetermined selection of bits of the binary classification dataset and sort its received predetermined selection of bits into an intermediary binary string in which the bits are ordered into a first group identifying addresses belonging to the identified subset, and a second group identifying addresses not belonging to the identified subset.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer y; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: A texture filtering unit has inputs arranged to receive at least two texture values each clock cycle and a plurality of filter coefficients, the plurality of filter coefficients relating to a plurality of different texture filtering methods; hardware logic arranged to convert the input texture values to fixed-point representation; a coefficient merging logic block arranged to generate a single composite filter coefficient for each input texture value from the plurality of filter coefficients; one multiplier for each input texture value, wherein each multiplier is arranged to multiply one of the input texture values by its corresponding single composite filter coefficient; an addition unit arranged to add together outputs from each of the multipliers; hardware logic arranged to convert an output from the addition unit back to floating-point format; and an output arranged to output the converted output from the addition unit.

Abstract: Systems and methods for monitoring and controlling access to a secured area are disclosed. A moveable barrier may be used in conjunction with one or more types of sensors and a logic unit to monitor and control access to the secured area. The barrier may permit access to the secured area when a set of access parameters are satisfied. A user at a human-machine interface may remotely communicate with persons detected at the secured area.

Abstract: A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2n±1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2n±1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for evaluating interactions with a user interface are disclosed. In one aspect, a method includes identifying a set of mutation events specifying changes to the structure of a user interface that occurred during the user session, and generating user interface states specifying different structures of the user interface throughout the given user session. Based at least in part on the user interface states, playback data that present visual changes of the user interface corresponding to the set of mutation events that occurred during the user session are generated. Session activity data describing user interactions that occurred during the user session are also generated. At least a portion of the playback data and the session activity data are output to a requesting device.

Abstract: A binary logic circuit for determining y=x mod(2m?1), where x is an n-bit integer, y is an m-bit integer, and n>m, includes reduction logic configured to reduce x to a sum of a first m-bit integer ? and a second m-bit integer ?; and addition logic configured to calculate an addition output represented by the m least significant bits of the following sum right-shifted by m: a first binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; a second binary value of length 2m, the m most significant bits and the m least significant bits each being the string of bit values represented by ?; and the binary value 1.

Abstract: A method for supplying electrical power to a gradient amplifier that drives a gradient coil for a magnetic resonance imaging system is provided. The method includes predicting a gradient voltage required to drive the gradient coil for a scan based at least in part on a gradient coil model. The method further includes calculating a voltage set point for a power supply based at least in part on the predicted gradient voltage. The method further includes providing electrical power to the gradient amplifier via the power supply based at least in part on the calculated voltage set point. The gradient coil model is based at least in part on historical data acquired prior to the scan.