Patents by Inventor Thomas S. Kanarsky
Thomas S. Kanarsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7989298Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.Type: GrantFiled: January 25, 2010Date of Patent: August 2, 2011Assignees: International Business Machines Corporation, Advanced Micro Devices, IncInventors: Kevin K. Chan, Brian J. Greene, Judson R. Holt, Jeffrey B. Johnson, Thomas S. Kanarsky, Jophy S. Koshy, Kevin McStay, Dae-Gyu Park, Johan W. Weijtmans, Frank B. Yang
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Publication number: 20110183486Abstract: A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses.Type: ApplicationFiled: January 25, 2010Publication date: July 28, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Kevin K. Chan, Brian J. Greene, Judson R. Holt, Jeffrey B. Johnson, Thomas S. Kanarsky, Jophy S. Koshy, Kevin McStay, Dae-Gyu Park, Johan W. Weijtmans, Frank B. Yang
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Patent number: 7968915Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.Type: GrantFiled: August 8, 2009Date of Patent: June 28, 2011Assignee: International Business Machines CorporationInventors: Thomas S. Kanarsky, Qiqing Ouyang, Haizhou Yin
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Patent number: 7871893Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.Type: GrantFiled: January 28, 2008Date of Patent: January 18, 2011Assignee: International Business Machines CorporationInventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
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Patent number: 7834399Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.Type: GrantFiled: June 5, 2007Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Thomas S. Kanarsky, Qiqing Ouyang, Haizhou Yin
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Publication number: 20090298297Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.Type: ApplicationFiled: August 8, 2009Publication date: December 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas S. Kanarsky, Qiqing Ouyang, Haizhou Yin
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Publication number: 20090242989Abstract: In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.Type: ApplicationFiled: March 25, 2008Publication date: October 1, 2009Inventors: KEVIN K. CHAN, Jack O. Chu, Jin-Ping Han, Thomas S. Kanarsky, Hung Y. Ng, Qiqing Quyang, Gen Pei, Chun-Yung Sung, Henry K. Utomo, Thomas A. Wallner
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Publication number: 20090189242Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.Type: ApplicationFiled: January 28, 2008Publication date: July 30, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
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Publication number: 20080303101Abstract: A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa.Type: ApplicationFiled: June 5, 2007Publication date: December 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Thomas S. Kanarsky, Qiqing Ouyang, Haizhou Yin
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Publication number: 20080083955Abstract: A stressed liner for improving carrier mobility in a transistor and a method for fabricating the same is disclosed. The stressed liner includes an intrinsically stressed conductive film encapsulated between two insulating layers such as silicon nitride, silicon oxide, or oxynitride. The stressed liner may be compressively-stressed or tensile-stressed depending on whether an n-FET or p-FET is required.Type: ApplicationFiled: October 4, 2006Publication date: April 10, 2008Inventors: Thomas S. Kanarsky, Qiqing Ouyang, Kathryn T. Schonenberg, Chun-Yung Sung
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Patent number: 7314789Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.Type: GrantFiled: December 30, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Xiao H. Liu, Huilong Zhu
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Patent number: 7250658Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: May 4, 2005Date of Patent: July 31, 2007Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Leong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 7211490Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.Type: GrantFiled: March 18, 2005Date of Patent: May 1, 2007Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong, Omer Dokumaci
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Patent number: 7173312Abstract: A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. The at least one NFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer, a Si-containing second gate electrode layer and a compressive metal, and the at least one PFET has a gate stack structure comprising a gate dielectric, a first gate electrode layer, a barrier layer and a tensile metal or a silicide.Type: GrantFiled: December 15, 2004Date of Patent: February 6, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Bruce B. Doris, Thomas S. Kanarsky, Xiao H. Liu, Huilong Zhu
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Patent number: 7041538Abstract: A high-performance recessed channel CMOS device including an SOI layer having a recessed channel region and adjoining extension implant regions and optional halo implant regions; and at least one gate region present atop the SOI layer and a method for fabricating the same are provided. The adjoining extension and optional halo implant regions have an abrupt lateral profile and are located beneath said gate region.Type: GrantFiled: November 14, 2003Date of Patent: May 9, 2006Assignee: International Business Machines CorporationInventors: Meikei Ieong, Omer H. Dokumaci, Thomas S. Kanarsky, Victor Ku
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Patent number: 7018891Abstract: Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.Type: GrantFiled: December 16, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Bruce B. Doris, MeiKei Ieong, Thomas S. Kanarsky
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Patent number: 6914303Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.Type: GrantFiled: August 28, 2003Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong, Omer Dokumaci
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Patent number: 6911383Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: June 26, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Patent number: 6905941Abstract: A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.Type: GrantFiled: June 2, 2003Date of Patent: June 14, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas S. Kanarsky, Meikei Ieong, Wesley C. Natzle
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Patent number: 6846734Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.Type: GrantFiled: November 20, 2002Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Ricky Amos, Katayun Barmak, Diane C. Boyd, Cyril Cabral, Jr., Meikei Leong, Thomas S. Kanarsky, Jakub Tadeusz Kedzierski