Patents by Inventor Thomas Sheppard

Thomas Sheppard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11743291
    Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: August 29, 2023
    Assignee: RIDGEBACK NETWORK DEFENSE, INC.
    Inventor: Thomas Sheppard Phillips
  • Patent number: 11587842
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: February 21, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Publication number: 20220231987
    Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 21, 2022
    Applicant: Ridgeback Network Defense, Inc.
    Inventor: Thomas Sheppard PHILLIPS
  • Patent number: 11310190
    Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 19, 2022
    Assignee: RIDGEBACK NETWORK DEFENSE, INC.
    Inventor: Thomas Sheppard Phillips
  • Publication number: 20210258346
    Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 19, 2021
    Applicant: Ridgeback Network Defense, Inc.
    Inventor: Thomas Sheppard PHILLIPS
  • Patent number: 10992707
    Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: April 27, 2021
    Assignee: RIDGEBACK NETWORK DEFENSE, INC.
    Inventor: Thomas Sheppard Phillips
  • Publication number: 20210043530
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Patent number: 10886189
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: January 5, 2021
    Assignee: Cree, Inc.
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Patent number: 10840162
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 17, 2020
    Assignee: Cree, Inc.
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Publication number: 20190312836
    Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.
    Type: Application
    Filed: December 6, 2018
    Publication date: October 10, 2019
    Applicant: Ridgeback Network Defense, Inc.
    Inventor: Thomas Sheppard PHILLIPS
  • Publication number: 20190259682
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Application
    Filed: May 1, 2019
    Publication date: August 22, 2019
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Patent number: 10367074
    Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 30, 2019
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
  • Patent number: 10332817
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Cree, Inc.
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Publication number: 20190182292
    Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 13, 2019
    Applicant: Ridgeback Network Defense, Inc.
    Inventor: Thomas Sheppard PHILLIPS
  • Publication number: 20190172769
    Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
  • Patent number: 9934983
    Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 3, 2018
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
  • Publication number: 20170012106
    Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
  • Patent number: 9490169
    Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: November 8, 2016
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
  • Publication number: 20150221574
    Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.
    Type: Application
    Filed: February 3, 2014
    Publication date: August 6, 2015
    Applicant: Cree, Inc.
    Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
  • Patent number: 8202796
    Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: June 19, 2012
    Assignee: Cree, Inc.
    Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner