Patents by Inventor Thomas Sheppard
Thomas Sheppard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11743291Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.Type: GrantFiled: April 26, 2021Date of Patent: August 29, 2023Assignee: RIDGEBACK NETWORK DEFENSE, INC.Inventor: Thomas Sheppard Phillips
-
Patent number: 11587842Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: October 29, 2020Date of Patent: February 21, 2023Assignee: Wolfspeed, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Publication number: 20220231987Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.Type: ApplicationFiled: March 29, 2022Publication date: July 21, 2022Applicant: Ridgeback Network Defense, Inc.Inventor: Thomas Sheppard PHILLIPS
-
Patent number: 11310190Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.Type: GrantFiled: December 6, 2018Date of Patent: April 19, 2022Assignee: RIDGEBACK NETWORK DEFENSE, INC.Inventor: Thomas Sheppard Phillips
-
Publication number: 20210258346Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.Type: ApplicationFiled: April 26, 2021Publication date: August 19, 2021Applicant: Ridgeback Network Defense, Inc.Inventor: Thomas Sheppard PHILLIPS
-
Patent number: 10992707Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.Type: GrantFiled: December 6, 2018Date of Patent: April 27, 2021Assignee: RIDGEBACK NETWORK DEFENSE, INC.Inventor: Thomas Sheppard Phillips
-
Publication number: 20210043530Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: October 29, 2020Publication date: February 11, 2021Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Patent number: 10886189Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: January 5, 2021Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Patent number: 10840162Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: May 1, 2019Date of Patent: November 17, 2020Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Publication number: 20190312836Abstract: A system and method detects or prevents tampering of computer networks by transmitting address messages indicating that unused network addresses are in use. The systems and method handles requests for network resources, such as Address Resolution Protocol (ARP) messages, and provides fabricated information to a potential attacker to disrupt an attack on an information system.Type: ApplicationFiled: December 6, 2018Publication date: October 10, 2019Applicant: Ridgeback Network Defense, Inc.Inventor: Thomas Sheppard PHILLIPS
-
Publication number: 20190259682Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Patent number: 10367074Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: September 26, 2016Date of Patent: July 30, 2019Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
-
Patent number: 10332817Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: GrantFiled: December 1, 2017Date of Patent: June 25, 2019Assignee: Cree, Inc.Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Publication number: 20190182292Abstract: Systems and methods mark or identify network data as being of interest by modifying the network data with a tag. A tag may be an unordered set of tag elements, and each tag element may be an ordered sequence of bits. For each data segment or packet transmitted, one or more fields of a network packet may be masked with a randomly chosen tag element.Type: ApplicationFiled: December 6, 2018Publication date: June 13, 2019Applicant: Ridgeback Network Defense, Inc.Inventor: Thomas Sheppard PHILLIPS
-
Publication number: 20190172769Abstract: A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.Type: ApplicationFiled: December 1, 2017Publication date: June 6, 2019Inventors: Chris Hardiman, Kyoung-Keun Lee, Fabian Radulescu, Daniel Namishia, Scott Thomas Sheppard
-
Patent number: 9934983Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: GrantFiled: February 3, 2014Date of Patent: April 3, 2018Assignee: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
-
Publication number: 20170012106Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
-
Patent number: 9490169Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: November 2, 2010Date of Patent: November 8, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
-
Publication number: 20150221574Abstract: A semiconductor device is configured to reduce stress in one or more film layers in the device. According to one embodiment, the semiconductor device includes a substrate, a discontinuous dielectric layer on a first surface of the substrate, and a substantially continuous encapsulation layer over the first surface of the substrate and the discontinuous dielectric layer. Notably, the dielectric layer may be broken into one or more dielectric sections in order to relieve stress in the semiconductor device.Type: ApplicationFiled: February 3, 2014Publication date: August 6, 2015Applicant: Cree, Inc.Inventors: Zoltan Ring, Donald A. Gajewski, Scott Thomas Sheppard, Daniel Namishia
-
Patent number: 8202796Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The polished surface of the silicon carbide substrate is then masked to define a predetermined location for at least one via that is opposite the device metal contact and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts. Finally, the via is metallized.Type: GrantFiled: February 7, 2011Date of Patent: June 19, 2012Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner