Abstract: A single-segment drive scheme for an electronic paper display (EPD) is replaced by a multiplexed drive scheme that reduces the number of driver pins to the number of display segments per digit or alphanumeric character plus one input/output (I/O) line per digit or alphanumeric character. In accordance with the invention, a passive digit selection mechanism enables a multiplex display drive scheme when the EPD material used typically has a stable threshold combined with a small hysteresis. Typically, display operation is better the smaller the hysteresis and the more stable the threshold of the EPD material that is used.

Abstract: A single-segment drive scheme for an electronic paper display (EPD) is replaced by a multiplexed drive scheme that reduces the number of driver pins to the number of display segments per digit or alphanumeric character plus one input/output (I/O) line per digit or alphanumeric character. In accordance with the invention, a passive digit selection mechanism enables a multiplex display drive scheme when the EPD material used typically has a stable threshold combined with a small hysteresis. Typically, display operation is better the smaller the hysteresis and the more stable the threshold of the EPD material that is used.

Abstract: A comb filter arrangement comprising at least one delay circuit and an adder, this adder being twice supplied with a video signal modulated on a carrier, which video signals are applied mutually shifted with time. The signals are delayed by the delay circuits, so that either video signal applied to the adder is delayed relative to the other video signal by a given period of time. Furthermore, the delay circuits are arranged in switched capacitor technique.

Abstract: In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit.

Abstract: The invention relates to a position sensor including at least two sensor units which measure in a contactless manner a position x of an element which is movably arranged relative to the sensor units. Using limited circuitry, the invention precludes sources of errors during the processing of the sensor signals in that from the sensor signals there is formed a measuring signal from the phase position of which relative to the clock signal there can be determined the position x. The position x may be, for example an angle or a length position.

Abstract: A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output.

Abstract: A counter and/or divider arrangement, comprising at least two subsidiary counter circuits, each of which comprises a number of flipflops which are concatenated in respect of their data inputs and outputs, all subsidiary counter circuits receiving a common clock signal, and also comprising at least one logic element, enables the implementation of arbitrary counting operations or division ratios with a low expenditure as regards circuitry and with low-noise operation in that in each logic element signals from the data output of one of the flipflops of at least a part of the subsidiary counter circuits are combined in conformity with an AND-function so as to form an associated resultant signal, each of the resultant signals being applied to at least one of the subsidiary counter circuits as a reset signal in order to switch the subsidiary circuit to an initial state, an output signal being formed from at least one of the resultant signals, the product of the total numbers of flipflops of all subsidiary counter c

Abstract: For a comb filter arrangement, for example, for separating a color picture signal into a modulated chrominance subcarrier and a luminance signal, while generating two comb filter function, a one-stage median filter (21) is provided in which the amplitudes of the simultaneously available signals of three picture lines and the two comb filter functions are compared with each other in a comparator stage which supplies logical comparison signals to a selection logic (30) in dependence upon the comparison results. The selection logic (30) constantly determines the signal having the middle instantaneous amplitude of the signals applied to the comparator stage on the basis of the comparison signals, and applies this signal to the medium filter output.