Abstract: Localized measurement of turbulent airflows is provided using enhanced techniques of digital holography with computed tomography. In an implementation, an optical beam is diffracted to produce an array of signal beams which propagate at different angles through a test volume that includes a test article. A reference beam is optically interfered with the array of signal beams after propagating through the test volume, producing a corresponding array of holograms simultaneously detected by a single digital holographic sensor. Digitized versions of the holograms are processed to produce a signal field for each test beam. Computed tomography is then applied to the signal fields to determine path-resolved turbulence measurements.

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Abstract: Embodiments are directed to sharing namespaces across file system clusters. A file in a spoke file system may be determined based on a command provided to the spoke file system such that the file may be associated with an inode mask. Data blocks associated with the file may be determined based on the command and the inode mask such that the data blocks may be absent from the spoke file system. Requests for leases may be generated based on the absent data blocks such that each lease request corresponds to a portion of the absent data blocks Employing the leases provided by a hub file system to: copy the absent data blocks from the hub file system where each portion of absent data blocks may be associated with a lease; updating the inode mask to include the leases and each copied portion of absent blocks.

Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Abstract: Technology is disclosed for improving read margin in a cross-point memory array. Drive transistors pass a read and write currents to the cross-point memory array. The read current charges a selected word line to turn on a threshold switching selector of a selected memory cell. While the threshold switching selector is on, the current (read or write) passes through the selected memory cell. The memory system applies a smaller overdrive voltage to the drive transistor when the drive transistor is passing the read current than when the drive transistor is passing the write current. A smaller overdrive voltage increases the resistance of the drive transistor which improves read margin. Increasing the resistance of the drive transistor increases the resistance seen by the threshold switching selector in the selected memory cell, which reduces the Ihold of the threshold switching selector. Reducing Ihold of the threshold switching selector improves read margin.

Abstract: A circuit is provided that includes a first transistor having a first terminal, a second terminal and a third terminal, and a second transistor comprising a first terminal, a second terminal and a third terminal. The first terminal of the first transistor comprises an input terminal of the circuit, the second terminal of the first transistor is coupled to a power supply bus, and the first transistor conducts a first current. The first terminal of the first transistor comprises an output terminal of the circuit, the second terminal of the second transistor is coupled to the power supply bus, and the third terminal of the second transistor is coupled to the third terminal of the first transistor. The second transistor conducts a second current proportional to the first current substantially independent of distance between the first transistor and the second transistor.

Abstract: A control circuit is configured to connect to a cross-point memory array in which each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET in a conductive state while the nMOSFET is in a non-conductive state. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be in a conductive state.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may turned on while the pMOSFET is turned off. The nMOSFET provides a higher resistance in place of the decreased resistance of the pMOSFET to amplify a signal at a sense circuit to allow accurate sensing of the voltage across the memory cell.

Abstract: Apparatuses and techniques are described for reading MRAM memory cells. In a cross-point memory array, each conductive line, such as a bit line or word line, is connected to a transistor pair comprising a pMOSFET in parallel with an nMOSFET. When selecting a memory cell to be read, a voltage of a first conductive line may be pulled up using the pMOSFET while a voltage of a second conductive line is pulled down, e.g., to 0 V, using the nMOSFET. This minimizes a capacitance while the selector is turned on. Further, when reading the selected memory cell, the parallel nMOSFET of the first conductive line may be turned on while the pMOSFET remains on. The nMOSFET adds a resistance which offsets a decreased resistance of the pMOSFET to allow accurate sensing of the voltage across the memory cell.

Abstract: In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM device, is connected in series with a threshold switching selector, such as an ovonic threshold switch. In a two-layer cross-point structure with such memory cells, the MRAM devices in one layer are inverted relative to the MRAM devices in the other layer. This can allow for the transient voltage spike placed across the MRAM device when the threshold switching selector first turns on in a sensing operation to dissipate more rapidly, reducing the risk of changing a stored data state before it can be sensed.

Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Abstract: Apparatuses and techniques are described for programming phase change memory cells while avoiding a clamp condition in transistors which are used for biasing a word line and bit line when the word line and bit line are unselected for a write operation. The transistors may be connected in parallel with the word line and bit line. During a write operation, a current source is connected to a selected word line and a voltage control circuit is connected to the selected bit line. The voltage control circuit can include a capacitor or a voltage driver, for example. The capacitor accumulates charge, or the voltage driver applies an increasing ramp voltage to the bit line, to increase the voltage of the bit line and word line during the write operation and to avoid the clamp condition.

Abstract: A computer having a processor and memory that stores instructions executable by the processor, wherein the computer is programmed to: receive adaptive transmission clutch data from a plurality of first vehicles, the data from each first vehicle including a modified shifting profile; determine, using the received data, an updated initial shifting profile; and provide the updated initial profile to a plurality of second vehicles.

Abstract: A computer having a processor and memory that stores instructions executable by the processor, wherein the computer is programmed to: receive adaptive transmission clutch data from a plurality of first vehicles, the data from each first vehicle including a modified shifting profile; determine, using the received data, an updated initial shifting profile; and provide the updated initial profile to a plurality of second vehicles.

Abstract: A continuously variable transmission includes a first shaft driveably connected to a power-plant and having a first pair of sheave disks, and a second shaft having a second pair of sheave disks. A tension member is connected to the first and second pairs of disks such that power is transmittable between the first and second shafts. A third shaft is selectively driveably connected to the second shaft via a clutch. The clutch includes an inner race fixed to one of the second and third shafts, and an outer race fixed to a gear and having an inner surface circumscribing the inner race. At least one pawl is biased to couple the races in a fixed relationship for common rotation. The clutch further includes an electric coil and an armature configured to engage the pawl to decouple the races in response to current being supplied to the electric coil.

Abstract: A continuously variable transmission includes a first shaft driveably connected to a power-plant and having a first pair of sheave disks, and a second shaft having a second pair of sheave disks. A tension member is connected to the first and second pairs of disks such that power is transmittable between the first and second shafts. A third shaft is selectively driveably connected to the second shaft via a clutch. The clutch includes an inner race fixed to one of the second and third shafts, and an outer race fixed to a gear and having an inner surface circumscribing the inner race. At least one pawl is biased to couple the races in a fixed relationship for common rotation. The clutch further includes an electric coil and an armature configured to engage the pawl to decouple the races in response to current being supplied to the electric coil.

Abstract: A vehicle including a continuously variable transmission including a gear selectively locked to an output shaft via a clutch actuated by an electric coil. The vehicle also includes a controller configured to, in response to wheel hop being detected, energize the coil to disengage the clutch allowing the gear and the output shaft to rotate independently of each other.

Abstract: A clutch module for a dual clutch transmission (DCT) is designed to improve circumferential fluid distribution to reduce or eliminate an unpleasant noise during engagement. In some embodiments, the reaction plate is restrained in a position offset 1-3 degrees from perpendicular to the housing axis. Consequently, 0.2-0.7 mm of clearance remains on one radial side of the clutch when all clearance has been removed on the other radial side of the clutch. Relative rotation between the hub and the housing pushes fluid from the tight side toward the loose side. In an alternative embodiment, the piston is designed to orient the pressure plate non-perpendicular to the housing axis.