Abstract: Techniques are disclosed that use an alternating current bridge circuit to determine whether an impedance change occurs at an input to DC-DC voltage converter(s). Techniques are also disclosed for a DC power distribution system that utilizes isolation circuitry coupled to an input of DC-DC voltage converter(s).

Abstract: A system, method and apparatus including a logic module, preferably embodied as an electronic card that operates in combination with a PC to correct errors caused by deficiencies existing in logic residing on the PC's motherboard, such as the PC's BIOS. The preferred logic card includes a transceiver module, a memory module (e.g. an EPROM or Masked ROM) containing storage elements and executable code stored as pages. The preferred logic card also includes a page register module in communication with the transceiver and the memory, and a paging mechanism that cooperates with the page register and the transceiver for allowing only a predetermined number of bytes (pages) of executable code to be accessible for operation in the PC's main-memory in order to correct errors caused by deficiencies existing in logic residing on the PC's motherboard.

Abstract: A computer system includes a microprocessor that is electrically connected to a first synchronous bus operating in synchronism with a first clock signal at a first clock frequency. A second synchronous bus operates in synchronism with a second clock signal at a second clock frequency and provides electrical communication to a number of peripheral devices. An asynchronous bus provides data communication between the first and second synchronous bus using handshaking signals so that the first and second clock signals operate independently of each other. The operating frequency and other parameters of the microprocessor and the first synchronous bus can be changed without requiring any changes to the second synchronous bus so that the microprocessor and the first synchronous bus can take advantage of advances in technology while allowing the second synchronous bus and the associated peripheral devices to remain compatible with previous versions of the computer system.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.