Abstract: Systems and methodologies associated with providing additional functionality to a conventional SAS expander are described. One exemplary SAS expander embodiment includes logic for selectively performing source identifier checking for frames received at the SAS expander. The logic may also facilitate selectively performing explicit route checking for frames received at the SAS expander. In one example, the logic may also facilitate selectively providing VLAN-like services to devices connected to the SAS expander.

Abstract: A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

Abstract: A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred.

Abstract: A multi-port adapter and method of operation suitable for use with serial ATA devices is disclosed. An adapter includes a switch that receives input from multiple host devices and an arbiter module for assigning a priority scheme to received commands. An outstanding request table is implemented as a memory module for storing identifying information associated with commands received from multiple host devices, and a free pointers queue is maintained to track slots available in the outstanding request table. A command tracker state machine decodes incoming requests from hosts, monitors the execution by these commands by the ATA device, and updates the memory module to reflect completion of commands. Also disclosed is a storage system including an adapter of the present invention and ATA storage devices.

Abstract: An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus.

Abstract: An embodiment of the present invention provides a peripheral controller for coupling a mass storage peripheral to a computer system. In a disclosed embodiment the peripheral controller is a disk array controller programmed for RAID. The peripheral controller includes a first messaging unit (FMU), a second messaging unit (SMU), and a peripheral interface which are connected by a local bus. The FMU responds to messages from a first operating system driver. The SMU responds to messages from a different second operating system driver. In one embodiment, the FMU responds to commands from the first operating system driver which is non-standard. In another embodiment, the SMU responds to commands from the second operating system driver which is compatible with the I2O standard. In the disclosed embodiment, the peripheral interface controls mass storage peripherals in response to messages sent to the FMU or the SMU.

Abstract: An embodiment of the present invention discloses a technique for concealing a peripheral memory transaction on a local bus within a peripheral controller from a host system bus. In the preferred embodiment both the local bus and the host system bus are PCI buses. The technique is implemented when a peripheral memory transaction is detected on the local bus. In a disclosed embodiment, the peripheral memory transaction is detected by monitoring command and byte enables (CBEs) and five upper address bits (AD[31::27]) of the local bus. A peripheral memory transaction is indicated when a memory transaction on the local bus is directed to an upper 128 MB of 4 GB host memory. When a memory transaction is detected to the upper 128 MB of memory the transaction is intercepted. The interception is accomplished by blocking the CBEs on the local bus from a peripheral interface.The peripheral interface in the preferred embodiment is a standard PCI--PCI bridge which couples the local bus to the host system bus.

Abstract: An embodiment of the present invention discloses a technique that allows hot plugging a peripheral controller card, containing both a local bus and a peripheral bus on a single connector, into a host system board containing a host system bus and a host I/O bus. When mating the peripheral controller card to the host system board a local device power supply (LDPS) is inactive, a peripheral device power bus (PDPB) is powered, and signal lines of a peripheral device are maintained in a high impedance state. Following a delay after the mating, the LDPS is activated by the host operating system (OS). Following the activation of the LDPS, the host system bus is coupled to the single connector through switches that are under OS control. In response to the activation of the LDPS, the signal lines of the peripheral device are enabled.In a disclosed embodiment the peripheral controller card is a disk array controller card, the local bus is a PCI bus, and the peripheral bus is a SCSI bus.

Abstract: The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor. Command/control information can be extracted from the point-to-point bus before data is transferred through the bridge circuit in order to allow the data to be acted on more quickly by processing/storage devices since the control data was already made available to the storage devices via the secondary channel.

Abstract: A FIFO with locked exchange capability is disclosed. The FIFO has a memory for storing and retrieving data submissions, a write address generator and a read address generator for sequentially addressing the memory. A difference counter maintains the difference between the number of writes to the queue and reads from the queue. The net difference, as tracked by the counter is a measure of the FIFO utilization. To detect the queue full condition, a comparator compares the maximum FIFO stack depth against the counter output. The result of this comparison is latched and provided to a write strobe generator so that, in a subsequent write operation, if the FIFO is full, the write strobe from the producer is blocked and the data will not be written to the FIFO. Otherwise, the write strobe from the producer is passed to the memory. Additionally, a remaining space count is maintained in a status register.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycle to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycles to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM.

Abstract: An apparatus and method for providing wait states using address bits not used in the device address decode. The upper address bits of a computer system are not used for peripheral and memory device decoding purposes. The unused bits are driven to indicate the desired number of wait states to be developed for each selected device, while still allowing a normal decode of the devices. Wait state and ready logic is provided which allows each device address to be assigned one of several possible wait state lengths by driving the most significant bits of the address. The address decode based wait state determination is overridden for RAM operations, and followed for ROM and peripheral operations.

Abstract: A SCSI bus controller which has a separate data path from the SCSI bus to the host bus and a separate command path for use to communicate with a local microprocessor. The local microprocessor is connected to a dual port RAM, the other port of which is connected to a bus master controller linked to the host system. Commands and status are passed via the dual port RAM. Data is passed through a FIFO. The local microprocessor does not have access to the data path but only controls direction of the data flow, the initiation of the sequence and the completion of the sequence.

Abstract: A disk array controller includes a local microprocessor, a bus master interface, a compatible interface, buffer memory and a disk interface. The controller includes a DMA controller between the microprocessor, the bus master interface, the compatibility interface and the buffer memory. DMA controllers are also provided between the disk interface and the buffer memory. One of these DMA channels includes an XOR engine used to develop parity information used with the disk array. The various DMA controllers are cycled to allow access to the buffer memory and the disk interface.

Abstract: An interface between a CPU bus and peripheral device such as a standard embedded controller disk drive uses either a dedicated, I/O mapped register set for control and status communication between the host CPU and the disk controller, or an alternate "flex mode" protocol which allows the drive to be used with great versatility in a wide variety of systems. This alternate "flex mode" protocol does not require changes to the hardware definition of the drive interface, but instead uses the data port to transfer information blocks to set up a subsequent data transfer through this port.

Abstract: Temperature sensors are located inside drive chambers where disk drives are located to signal an overheating condition. An overheating condition triggers external alarms and produces an interrupt signal to the disk drive controller, which, in turn, alerts the operating system. If the operating system does not comprehend the problem and take the appropriate action, the controller shuts down the disk drives after a certain period of time.