Abstract: Examples of circuits and methods are provided for common mode stability and bandwidth broadening. A current generator circuit may include a first and a second transistor. Each of the first and second transistors includes a first, second, and third terminal. The first and second transistors provide a first and a second output current at their corresponding third terminals. A first branch including a first resistor and a first capacitor coupled in series is coupled between the third terminal of the first transistor and the first terminal of the second transistor. A second branch including a second resistor and a second capacitor coupled in series is coupled between the third terminal of the second transistor and the first terminal of the first transistor. The first and the second branches are configured to enable the current generator circuit to provide the first and second currents with improved common mode stability.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A serializer may include a serdes framer interface (SFI) circuit, a clock multiplier unit, and a multiplexing circuit. A deserializer may include an input receiver circuit for receiving and adjusting an input data signal, a clock and data recovery circuit (CDR) for recovering clock and data signals, a demultiplexing circuit for splitting one or more data channels into a higher number of data channels, and a serdes framer interface (SFI) circuit for generating a reference channel and generating output data channels to be sent to a framer. The input receiver circuit may include a limiting amplifier. Each of the serializer and deserializer may further include a pseudo random pattern generator and error checker unit. The serializer and deserializer each may be integrated into its respective semiconductor chip or both may be integrated into a single semiconductor chip.

Abstract: An integrated circuit includes a serdes framer interface (SFI) circuit for receiving a first set of data channels and a reference channel, generating first logic levels for the first set of data channels, and realigning the first set of data channels relative to a reference channel. The integrated circuit further includes a multiplexing circuit for receiving a second set of data channels and for merging the second set of data channels into one or more data channels. The second set of data channels is generated based on the first set of data channels. A data rate of the one or more data channels is higher than a data rate of the second set of data channels.

Abstract: According to one embodiment of the invention, a ring oscillator is provided that includes a number of stages, each of the stages being coupled to an output of at least two previous stages. This architecture is referred to hereinafter as a “feed forward” architecture, as signals are fed forward to further stages beyond a consecutive stage. Any number of stages may be used. This architecture represents a new topology for ring oscillator design, as ring oscillators generally include consecutive stages that each have an input from the previous stage only. In general, such an architecture achieves higher frequencies than oscillators without feed forward paths.

Abstract: High-speed, high-performance, low-power transponders, serializers and deserializers are disclosed. A transponder may include a transmitter and a receiver. A serializer may include (i) a serdes framer interface (SFI) circuit for receiving data channels and a reference channel from a framer and realigning the data channels, (ii) a clock multiplier unit (CMU) for receiving a clock frequency and translating the clock frequency to a higher-clock frequency, (iii) a multiplexing circuit for merging data channels into one data channel, (iv) an output driver stage, (v) a reference selection circuit for selecting a reference clock, filtering the reference clock, and providing to the CMU one of the selected reference clock or a filtered reference clock.

Abstract: A quadrature ring oscillator for high clock-rate applications is disclosed. A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers to provide consistent oscillation even at high clock rates. One stage of the quadrature ring oscillator comprises a first resonating element having an input and an output, and a first variable summer having L and P inputs and an output, with its L input being connected to the output of the first resonating element. The output of the first variable summer is connected to the input of the first resonating element The first variable summer may generate its output at a first phase by combining the L and P inputs. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and an output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element.

Abstract: A quadrature ring oscillator for high clock-rate applications is disclosed. A quadrature LC ring oscillator may use two stages of LC oscillators and variable mixers to provide consistent oscillation even at high clock rates. One stage of the quadrature ring oscillator comprises a first resonating element having an input and an output, and a first variable summer having L and P inputs and an output, with its L input being connected to the output of the first resonating element. The output of the first variable summer is connected to the input of the first resonating element. The first variable summer may generate its output at a first phase by combining the L and P inputs. A second stage of the LC ring oscillator comprises a second resonating element, which has an input and an output, with its output being connected to the P input of the first variable summer. An inverter is used to produce an inverted signal of the output of the first resonating element.

Abstract: A multiplexer is provided that is symmetric in that substantially the same delay is experienced from any input of the multiplexer to the multiplexer output. It is realized that in conventional serial transmission systems, standard Current Mode Logic (CML) multiplexers are used which are asymmetric and exhibit different delays between select and data inputs. Because of these delays, conventional transmission systems experience jitter at high frequencies. To extend the operable range of communication systems, a symmetric multiplexer may be used which has substantially the same delay from any input to the multiplexed output, thus reducing jitter. For example, the multiplexer may be part of a communication system having a serial data transmission circuit.