Abstract: A floating point arithmetic unit is provided which effectuates arithmetic operations upon floating point numbers. A comparator unit, which may be implemented using a carry-skip chain, determines the relative magnitudes of the exponents of the floating point numbers to be operated upon. A first ripple carry subtractor unit formed within a first ripple carry shifter subtracts a first value corresponding to the exponent of a first of the floating point numbers from a second value corresponding to the exponent of a second of the floating point numbers. A second ripple carry subtractor unit formed within a second ripple carry shifter subtracts the second value from the first value. When certain lower order bit results of the exponent value subtraction operations of each ripple carry subtractor are obtained, the mantissa of the floating point number with the smaller exponent provided to one of the carry ripple shifters is shifted to the right by a number of positions dependent upon the lower order bit results.

Abstract: A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point unit. When the reorder buffer detects a floating point instruction which is ready to be retired, the reorder buffer pulses the retire signal. When the floating point unit executes the floating point instruction and produces a corresponding instruction result, the floating point unit pulses the valid signal. Upon assertion of both the retire signal and the valid signal, the floating point instruction is retired by the floating point unit. The reorder buffer retires the floating point instruction upon asserting the retire signal. Either the valid signal or the retire signal may be asserted first (in a temporal sense) for the floating point instruction. The receiving unit for the signal asserted first stores the signal in a shift register until the receiving unit detects the particular floating point instruction.

Abstract: A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating point operations and one or more integer operations such as memory load operations. The floating point operations are conveyed to the floating point unit. The memory load operations load the floating point operands of the floating point operations. Floating point operands that are wider than integer operands are handled by multiple memory load operations. Each memory load operation loads a portion of the floating point operand. The portions of the floating point operand are combined is a queue in the floating point unit. When the floating point unit has received the floating point operation and the memory operands that comprise with the floating point operand, the floating point unit dispatches the floating point instruction for execution.

Abstract: A microprocessor is provided which includes a heuristic processing unit configured to detect a predefined group of instructions and to cause the performance of a specific function associated with the group of instructions. The specific function may correspond to the outcome of executing the group of instructions. Alternatively, the specific function may be a set of operations not directly corresponding to the group of instructions, but designed to improve the performance of the sequence of instructions within which the group of instructions is embedded. The heuristic processing unit asserts control signals to dedicated hardware to cause the specific function to be performed. Instruction sequences need not be modified from the instruction set employed by the microprocessor. The microprocessor detects the previously inefficient instruction sequences and performs the corresponding function efficiently.

Abstract: A microprocessor implements a hierarchical microcode implementation for floating point instructions. Floating point instructions are classified as microcode instructions. The microcode unit parses the floating point instructions into one or more floating point operations and one or more integer operations such as memory load operations. The floating point operations are conveyed to the floating point unit. The memory load operations load the floating point operands of the floating point operations. Floating point operands that are wider than integer operands are handled by multiple memory load operations. Each memory load operation loads a portion of the floating point operand. The portions of the floating point operand are combined is a queue in the floating point unit. When the floating point unit has received the floating point operation and the memory operands that comprise with the floating point operand, the floating point unit dispatches the floating point instruction for execution.

Abstract: A cache is provided which prefetches data words associated with a particular addressing mode. When a data word is accessed in response to the execution of an instruction, the data word is discarded by the cache. Data which is accessed in a use-once fashion (such as DSP data, for example) may be thereby available with cache-hit memory access times instead of main memory access times. The present cache prefetches data words spaced at regular or irregular intervals, wherein the interval is specified by the addressing mode of the instruction. Multiple words within a data stream may be successfully prefetched. The cache described herein may be incorporated into a microprocessor having a conventional cache as well. Data which is indicated to be used once may be stored in the present cache, while data exhibiting locality may be stored in the conventional cache. Data which exhibits locality is thereby retained within the cache system when use-once data is accessed.

Abstract: A computer system is provided which includes at least two microprocessors. The first microprocessor is configured to translate instructions from an original computer program coded in a first instruction set to a translated computer program coded in a second instruction set. The second microprocessor is configured to execute the translated program. In one particular embodiment, the original program is coded in the x86 instruction set and the translated program is coded in the ADSP 2171 instruction set. Instead of manually performing the translation, the translation is automatically performed by the computer system upon invocation of the original computer program. Those computer programs which may be more efficiently executed by the second microprocessor may be translated into the instruction set executed by the second microprocessor. In one embodiment, the translation of the computer program is performed in page-sized portions. The first microprocessor translates a first page of the original computer program.

Abstract: A processor employing a dynamically configurable bus interconnect is provided. The interconnect routes data between functional units and memories included within the processor in response to an instruction field. As opposed to a particular hard-wired interconnect, the dynamically variable interconnect may be modified to form an optimum interconnect for the particular algorithm being executed. Still further, the interconnect may be modified between several configurations during the execution of the algorithm, as often as each clock cycle. Because an instruction field is used to directly specify the configuration of the interconnect during execution of that instruction, control over the interconnect is afforded to the programmer writing the code which implements a particular algorithm.

Abstract: A microprocessor including an instruction decode unit configured to detect a DSP call instruction is provided. The DSP call instruction is indicative of a call to a subroutine which performs a DSP function. Detected DSP call instructions are routed to a DSP which executes a routine performing the corresponding function. Subsequent to the DSP completing execution of the routine, the microprocessor continues execution at the instruction subsequent to the DSP call instruction. If a DSP is not included in the computer system, the DSP call instruction is executed in a manner similar to a subroutine call instruction. The microprocessor subsequently executes a corresponding routine which performs the DSP function.

Abstract: A high speed adder suitable for incorporation into electronic digital processing circuits includes at least one first independent adder assuming a carry in of zero (0); at least one second independent adder assuming a carry in of one (1); carry prediction logic circuitry for producing carries for the first and second independent adders, which carry prediction logic circuitry is operable simultaneously with the first and second independent adders; and a final mux for producing a correct result based upon outputs received from the first and second independent adders and the carry prediction logic circuitry.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: A special carry save adder includes structure for performing multiple addition operations, common input structure to the structure for performing multiple addition operations, and mixing structure for selecting the desired result of the multiple addition operations.

Abstract: An apparatus for performing the division of a first operand by a second operand by iteratively producing a series of partial remainders and predicted quotient bits utilizing the generation of multiples of the second operand and the selection of one of the generated multiples. The second operand is first selected as a first partial remainder. A first quotient bit is predicted from the first and second operands and a next quotient bit is predicted from the partial remainder and the second operand. One of the generated multiples is selected for producing a next partial remainder based upon the next quotient prediction. A next partial remainder is then produced from the produced partial remainder and the selected multiple of the second operand.

Abstract: A high radix carry lookahead tree includes a plurality of tree nodes, each of the tree nodes including a carrying chain or a variation thereof, and/or a NAND gate chain or a variation thereof; and each tree node may have three or more children.

Abstract: A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent.

Abstract: A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.