Patents by Inventor Thomas W. Mountsier
Thomas W. Mountsier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10242883Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.Type: GrantFiled: June 23, 2017Date of Patent: March 26, 2019Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Publication number: 20180374712Abstract: A method for etching features in an OMOM stack with first layer of silicon oxide, a second layer of a metal containing material over the first layer, a third layer of silicon oxide over the second layer, and a fourth layer of a metal containing material over the third layer is provided. A hardmask is formed over the stack. The hardmask is patterned. The OMOM stack is etched through the hardmask.Type: ApplicationFiled: June 23, 2017Publication date: December 27, 2018Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Patent number: 9659783Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: GrantFiled: March 27, 2015Date of Patent: May 23, 2017Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Patent number: 9230800Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.Type: GrantFiled: March 31, 2014Date of Patent: January 5, 2016Assignee: Novellus Systems, Inc.Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
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Publication number: 20150200106Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: ApplicationFiled: March 27, 2015Publication date: July 16, 2015Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Patent number: 9018103Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: GrantFiled: September 26, 2013Date of Patent: April 28, 2015Assignee: Lam Research CorporationInventors: Joydeep Guha, Sirish K. Reddy, Kaushik Chattopadhyay, Thomas W. Mountsier, Aaron Eppler, Thorsten Lill, Vahid Vahedi, Harmeet Singh
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Publication number: 20150087154Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Inventors: Joydeep GUHA, Sirish K. REDDY, Kaushik CHATTOPADHYAY, Thomas W. MOUNTSIER, Aaron EPPLER, Thorsten LILL, Vahid VAHEDI, Harmeet SINGH
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Publication number: 20140209562Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: Novellus Systems, Inc.Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
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Patent number: 8728956Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.Type: GrantFiled: April 11, 2011Date of Patent: May 20, 2014Assignee: Novellus Systems, Inc.Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
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Patent number: 8053861Abstract: Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.Type: GrantFiled: January 26, 2009Date of Patent: November 8, 2011Assignee: Novellus Systems, Inc.Inventors: Thomas W. Mountsier, Roey Shaviv, Steven T. Mayer, Ronald A. Powell
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Publication number: 20110256726Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.Type: ApplicationFiled: April 11, 2011Publication date: October 20, 2011Inventors: Adrien LaVoie, Shankar Swaminathan, Hu Kang, Ramesh Chandrasekharan, Tom Dorsh, Dennis M. Hausmann, Jon Henri, Thomas Jewell, Ming Li, Bryan Schlief, Antonio Xavier, Thomas W. Mountsier, Bart J. van Schravendijk, Easwar Srinivasan, Mandyam Sriram
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Patent number: 8030777Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.Type: GrantFiled: February 5, 2007Date of Patent: October 4, 2011Assignee: Novellus Systems, Inc.Inventors: Bart van Schravendijk, Thomas W Mountsier, Mahesh K Sanganeria, Glenn B Alers, Roey Shaviv
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Patent number: 7842604Abstract: The present invention provides a low dielectric constant copper diffusion barrier film composed, at least in part, of boron-doped silicon carbide suitable for use in a semiconductor device and methods for fabricating such a film. The copper diffusion barrier maintains a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.Type: GrantFiled: May 22, 2007Date of Patent: November 30, 2010Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Atul Gupta, Karen Billington, Michael Carris, William Crew, Thomas W. Mountsier
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Publication number: 20100187693Abstract: Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.Type: ApplicationFiled: January 26, 2009Publication date: July 29, 2010Inventors: Thomas W. Mountsier, Roey Shaviv, Steven T. Mayer, Ronald A. Powell
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Patent number: 7420275Abstract: Copper diffusion barrier films having a boron-doped silicon carbide layer with at least 25% boron by atomic weight of the layer composition have advantages for semiconductor device integration schemes. The films have an integration worthy etch selectivity to carbon doped oxide of at least 10 to 1, can adhere to copper with an adhesion energy of at least 20 J/m2, and can maintain an effective dielectric constant of less than 4.5 in the presence of atmospheric moisture. The films are suitable for use in a wide range of VLSI and ULSI structures and devices.Type: GrantFiled: March 8, 2006Date of Patent: September 2, 2008Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Atul Gupta, Karen Billington, Michael Carris, William Crew, Thomas W. Mountsier
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Patent number: 7396759Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.Type: GrantFiled: November 3, 2004Date of Patent: July 8, 2008Assignee: Novellus Systems, Inc.Inventors: Bart van Schravendijk, Thomas W Mountsier, Mahesh K Sanganeria, Glenn B Alers, Roey Shaviv
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Patent number: 7239017Abstract: The present invention provides a low dielectric constant copper diffusion barrier film composed, at least in part, of boron-doped silicon carbide suitable for use in a semiconductor device and methods for fabricating such a film. The copper diffusion barrier maintains a stable dielectric constant of less than 4.5 in the presence of atmospheric moisture.Type: GrantFiled: August 9, 2004Date of Patent: July 3, 2007Assignee: Novellus Systems, Inc.Inventors: Yongsik Yu, Atul Gupta, Karen Billington, Michael Carris, William Crew, Thomas W. Mountsier
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Patent number: 6875699Abstract: A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.Type: GrantFiled: May 1, 2002Date of Patent: April 5, 2005Assignees: Lam Research Corporation, Novellus Sytems, Inc.Inventors: Stephan Lassig, S. M. Reza Sadjadi, Vinay Pohray, Si Yi Li, Thomas W. Mountsier, Chiu Chi
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Patent number: 6265320Abstract: A method of limiting surface damage during reactive ion etching of an organic polymer layer on a semiconductor substrate combines particular choices of process gases and plasma conditions with a post-etch passivation treatment. According to the method, a low density plasma etcher is used with a process gas mixture of one or more of an inert gas such as argon, helium, or nitrogen; methane; hydrogen; and oxygen, where the percentage of oxygen is up to about 5%. Typically a parallel plate plasma etcher is used. The reactive ion etching is followed by a post-etch passivation treatment in a which a gas containing hydrogen is flowed over the etched layer at an elevated temperature. The method is particularly useful in reactive ion etching of fluorinated organic polymer layers such as films formed from parylene AF4, and layers of poly(arylene ethers) and TEFLON®.Type: GrantFiled: December 21, 1999Date of Patent: July 24, 2001Assignee: Novellus Systems, Inc.Inventors: Jianou Shi, Thomas W. Mountsier, Mary Anne Plano, Joseph R. Laia
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Patent number: 6200412Abstract: A plasma-enhanced chemical vapor deposition system includes a number of process gas injection tubes and at least one dedicated clean gas injection tube. A plasma is used to periodically clean the interior surfaces of the deposition chamber. The cleaning is made more rapid and effective by introducing the clean gas through the dedicated clean gas injection tube. In this manner the clean gas can be introduced at a relatively high flow rate without detracting from the cleaning of the interior surfaces of the process gas injection tubes. As a separate aspect of this invention, a high-frequency signal is applied to both terminals of the coil during the cleaning process. This produces a plasma, mainly by capacitive coupling, which has a shape and uniformity that are well-suited to cleaning the surfaces of the deposition chamber.Type: GrantFiled: February 16, 1996Date of Patent: March 13, 2001Assignee: Novellus Systems, Inc.Inventors: Michael D. Kilgore, Wilbert G. M. van den Hoek, Christopher J. Rau, Bart J. van Schravendijk, Jeffrey A. Tobin, Thomas W. Mountsier, James C. Oswalt