Abstract: A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.

Abstract: A bus arbitration system comprising a plurality of bus lines and a clock which produces first and second phrases in which a drive generates a first logic state during the first phase to precharge the capacitance associated with the bus lines and generates either first or second logic state during the second phase. Also, a bus interface is described in which different types of information are transmitted during different phases.

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.