Abstract: Methods and systems for division operation are described. A processor can initialize an estimated quotient between the dividend and the divisor separately from a floating-point unit (FPU) pipeline. The processor can implement the FPU pipeline to execute a refinement process that can include at least a first iteration of operations and a second iteration of operations. The refinement process can include, in the first iteration of operations, generating a first unnormalized floating-point value using the initialized estimated quotient. The refinement process can include, in the second iteration of operations, generating a second unnormalized floating-point value using the first unnormalized floating-point value. The processor can determine a final quotient based on the second unnormalized floating-point value.

Abstract: Methods and systems for division operation are described. A processor can initialize an estimated quotient between the dividend and the divisor separately from a floating-point unit (FPU) pipeline. The processor can implement the FPU pipeline to execute a refinement process that can include at least a first iteration of operations and a second iteration of operations. The refinement process can include, in the first iteration of operations, generating a first unnormalized floating-point value using the initialized estimated quotient. The refinement process can include, in the second iteration of operations, generating a second unnormalized floating-point value using the first unnormalized floating-point value. The processor can determine a final quotient based on the second unnormalized floating-point value.

Abstract: A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the composite VLIW instruction to perform the operation.

Abstract: A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

Abstract: A processor core includes a storage device which stores a composite very large instruction word (VLIW) instruction, an instruction unit which obtains the composite VLIW instruction from the storage device and decodes the composite VLIW instruction to determine an operation to perform, and a composite VLIW instruction execution unit which executes the decoded composite VLIW instruction to perform the operation.

Abstract: A fully programmable graphics processing engine is provided. The graphics processing engine includes three independent, programmable processors that run independent sets of instructions from independent instruction storage facilities. Graphics processing tasks may be distributed among the serially pipelined processors to allow for load balancing and parallel processing. The graphics processing engine may be a graphics co-processing core within a larger, general purpose computing system. Register files and storage units may be addressable by the system host processor. Each processor accepts incoming data for state or context updates. Each processor may execute a specific graphics processing function by executing a set of instructions when a predetermined memory address is accessed.

Abstract: A method and apparatus in a data processing system for processing graphics data in a processing element. A command is received. A determination is then made as to whether the command affects processing of current graphics data within the processing element. The command is sent to a subsequent processing element if the processing element is unaffected by the command. The command is held without affecting the processing element if the command affects processing of the current graphics data within the processing element until processing of the current graphics data has completed.

Abstract: A floating point exponentiation circuit suitable for calculating the value BE is disclosed where B and E are floating point values. The floating point exponentiation circuit includes circuitry for producing a value P, where P is approximately equal to E*((BEXP−127)+log2(1.BMAN), BEXP is an exponent field of the base B, and 1.BMAN is a 24-bit mantissa field of the base B. The floating point exponentiation circuit further includes circuitry for adjusting the value P wherein the floating point representation of the adjusted value of P includes a mantissa field that indicates an integer portion Pi of P and a fractional portion Pf of P.

Abstract: A floating point inverse square root circuit is disclosed. The circuit is configured to receive a floating point value comprised of a sign bit, an exponent field, and a mantissa field. The inverse square root circuit includes a lookup table configured to receive at least a portion of the floating point value and further configured to generate an initial approximation (x0) of the inverse square root of the floating point value from the received portion of the floating point value. The inverse square root circuit further includes a first estimation circuit that receives the initial approximation from the lookup table and at least a portion of a value L derived from the floating point value mantissa field (M) and further configured to produce a first approximation (x1) of the floating point value's inverse square root based upon L and x0 where x1 is a more accurate estimate of the inverse square root than x0.

Abstract: Lighting parameters are received as floating-point numbers from a software application via an application programming interface (API). The floating-point numbers are converted to a fixed-point representation having a preselected number of bits. The number of bits is selected in accordance with a predetermined number of bits required by a frame buffer, which thus establishes the number of color values supported by the graphics display system. In order to preserve accuracy to within the number of bits in each value in the frame buffer, the representation in the fixed-point engine includes additional bits relative to the number of bits in the color values sent to the frame buffer. Floating-point values received via the graphics API are converted to fixed-point representations by first prescaling the floating-point values.

Abstract: A graphics pipeline receives graphics data at an input. Processed graphics data is transmitted at an output of the graphics pipeline. A plurality of stages are present in the graphics pipeline. A first stage within the plurality of stages is connected to the input and a last stage within the plurality of stages is connected to the output. A selected stage within the plurality of stages includes a plurality of modes of operation including a first mode of operation, responsive to receiving a first signal in which the selected stage is enabled to process graphics data received by the stage. A second mode of operation occurs in response to receiving a second signal, the selected stage is disabled and data received from a prior stage within the plurality of stages is passed through to a subsequent stage within the plurality of stages.

Abstract: A lighting circuit for use in a graphics adapter of a data processing system is disclosed. The circuit includes a geometry stage configured to receive the coordinates of a graphic primitive vertex and the vertex's normal vector. The circuit may calculate a first set of values equal to the dot product of the normal vector and a unit vector from the vertex to a corresponding light source, a second set of values equal to the dot product of the normal vector and a unit half vector, and a third set of values equal to the product of an attenuation factor associated with each light source and a spotlight factor associated with each light source. The lighting circuit further includes a color stage for receiving the first, second, and third sets of values from the geometry stage and further configured to calculate a primary vertex color based thereon.

Abstract: An apparatus and method for three-dimensional graphic rendering are implemented. For each vertex on a surface of a graphic to be rendered, the scalar product of the unit normal to the surface and a half vector (the vector bisecting an angle between a unit vector in a direction of observation, the “eye” vector and a unit vector in a direction of a light source, the “light vector”), is generated outside of a graphics engine. Additionally, a second scalar product, between the unit normal and the unit vector in the direction of the light source is generated. These scalar products are loaded into two predetermined components of the unit normal, and sent to the graphics engine in lieu of the corresponding values of the components of the unit normal. In the graphics engine, components of the light vector and the half vector are assigned respective predetermined values, wherein the calculation of the two scalar products by the graphics engine produces the correct results.

Abstract: A graphics adapter capable of supporting lighting models from multiple Application Programming, Interfaces (APIs) within a graphics system is disclosed. The graphics adapter includes a dot product machine and a control means. The dot product machine can perform geometry computations regardless of the API format in which the graphics data is expressed. The control means is utilized to multiplex between a set of graphics data having a first API format and a set of graphics data having a second API format in order to determine the inputs of the dot product machine. As a result, lighting models from multiple APIs can be supported by a single graphics adapter.

Abstract: A graphics adapter having a versatile lighting engine is disclosed. The graphics adapter generates graphics objects in a graphics scene. Each of the graphics objects within the graphics scene is made up of a number of polygons that are delimited by a set of vertices. The graphics adapter includes a graphics pipeline and a control module. In response to attributes received from a graphics software application, the control module selectively controls a frequency in which vertices are fed into the graphics pipeline and controls a number of concurrent calculations that are performed on the vertices within the graphics pipeline.