Patents by Inventor Thorsten Lill
Thorsten Lill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11832533Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.Type: GrantFiled: December 20, 2021Date of Patent: November 28, 2023Assignee: Lam Research CorporationInventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
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Patent number: 11792987Abstract: A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.Type: GrantFiled: October 22, 2019Date of Patent: October 17, 2023Assignee: LAM RESEARCH CORPORATIONInventors: Thorsten Lill, Meihua Shen, John Hoang, Hui-Jung Wu, Gereng Gunawan, Yang Pan
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Publication number: 20230298904Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.Type: ApplicationFiled: March 21, 2023Publication date: September 21, 2023Inventors: Ivan L. Berry, III, Thorsten Lill, Andreas Fischer
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Patent number: 11637022Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.Type: GrantFiled: July 3, 2019Date of Patent: April 25, 2023Assignee: Lam Research CorporationInventors: Ivan L. Berry, III, Thorsten Lill, Andreas Fischer
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Patent number: 11520953Abstract: Etch in a thermal etch reaction is predicted using a machine learning model. Chemical characteristics of an etch process and associated energies in one or more reaction pathways of a given thermal etch reaction are identified using a quantum mechanical simulation. Labels indicative of etch characteristics may be associated with the chemical characteristics and associated energies of the given thermal etch reaction. The machine learning model can be trained using chemical characteristics and associated energies as independent variables and labels as dependent variables across many different etch reactions of different types. When chemical characteristics and associated energies for a new thermal etch reaction are provided as inputs in the machine learning model, the machine learning model can accurately predict etch characteristics of the new thermal etch reaction as outputs.Type: GrantFiled: May 3, 2018Date of Patent: December 6, 2022Assignee: Lam Research CorporationInventors: Thorsten Lill, Andreas Fischer, Ivan L. Berry, III, Nerissa Sue Draeger, Richard A. Gottscho
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Publication number: 20220293431Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.Type: ApplicationFiled: June 2, 2022Publication date: September 15, 2022Inventors: Theodoros Panagopoulos, Andreas Fischer, Thorsten Lill
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Patent number: 11380556Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include supporting and thermally floating a substrate in a processing chamber, modifying one or more surface layers of material on the substrate by chemical adsorption, without using a plasma, while the substrate is maintained at a first temperature, and removing the one or more modified surface layers by desorption, without using a plasma, while the substrate is maintained at a second temperature, the first temperature being different than the second temperature. An apparatus may include a processing chamber and support features configured to support and thermally float a substrate in the chamber, a process gas unit configured to flow a first process gas onto the substrate, a substrate heating unit configured to heat the substrate, and a substrate cooling unit configured to actively cool the substrate.Type: GrantFiled: November 24, 2020Date of Patent: July 5, 2022Assignee: Lam Research CorporationInventors: Theodoros Panagopoulos, Andreas Fischer, Thorsten Lill
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Publication number: 20220186734Abstract: A processing chamber and method of etching a semi-conductor substrate are presented. The processing chamber is symmetric, with the centerlines of a chuck and stem of a stage to retain a semi-conductor substrate aligned with a centerline of a passage in a core of a pump used to evacuate the processing chamber and with a center-line of a gas port through which gas is introduced to the processing chamber. The stem extends through the passage and a spiral groove is formed in the passage in only one of the stem or an inner surface of the core to provide pumping action to counter back streaming of the gas from an exhaust of the pump in an intermediate and viscous flow regime inside a gap between the stem and the core.Type: ApplicationFiled: March 13, 2020Publication date: June 16, 2022Inventors: Thorsten Lill, Mariusch Gregor
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Publication number: 20220171370Abstract: A high density, controlled integrated circuits factory having process modules occupying approximately two-thirds of the factory floor space with the remaining one-third of the factory floor space being used for servicing the process modules and for loading and unloading wafers to and from the process modules. A subfloor is provided below the factory floor to allow service lifts to travel across the factory. Service lifts can be raised to the factory floor level to service process modules. Overhead lines are also provided over the process modules to transport service items as well as wafers across the factory.Type: ApplicationFiled: April 16, 2020Publication date: June 2, 2022Inventors: Thorsten LILL, Mariusch GREGOR, Candi KRISTOFFERSEN
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Publication number: 20220165546Abstract: High aspect ratio features are etched using a plasma etching apparatus that can alternate between accelerating negative ions of reactive species at a low energy and accelerating positive ions of inert gas species at a high energy. The plasma etching apparatus can be divided into at least two regions that separate a plasma-generating space from an ionization space. Negative ions of the reactive species can be generated by electron attachment ionization in the ionization space when a plasma is ignited in the plasma-generating space. Positive ions of the inert gas species can be generated by Penning ionization in the ionization space when the plasma is quenched in the plasma-generating space.Type: ApplicationFiled: March 6, 2020Publication date: May 26, 2022Inventors: Thorsten Lill, Ivan L. Berry, III, Theodoros Panagopoulos
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Publication number: 20220131071Abstract: Patterned magnetoresistive random access memory (MRAM) stacks are formed by performing a main etch through a plurality of MRAM layers disposed on a substrate, where the main etch includes using ion beam etching (IBE). After the main etch, gapfill dielectric material is deposited in spaces between the patterned MRAM stacks, and the gapfill dielectric material is selectively etched or otherwise formed to an etch depth that is above a depth of an underlayer. After the gapfill dielectric material is formed, at least some of the gapfill dielectric material and any electrically conductive materials deposited on sidewalls of the patterned MRAM stacks are removed by performing an IBE trim etch.Type: ApplicationFiled: February 26, 2020Publication date: April 28, 2022Applicants: Lam Research Corporation, Lam Research CorporationInventors: Thorsten Lill, Ivan L. Berry, III
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Publication number: 20220115592Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
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Patent number: 11289306Abstract: The embodiments herein relate to methods and apparatus for etching features in semiconductor substrates. In a number of cases, the features may be etched while forming a spin-torque-transfer random access memory (STT-RAM) device. In various embodiments, the substrate may be cooled to a low temperature via a cooled substrate support during particular processing steps. The cooled substrate support may have beneficial impacts in terms of reducing the degree of diffusion-related damage in a resulting device. Further, the use of a non-cooled substrate support during certain other processing steps can likewise have beneficial impacts in terms of reducing diffusion-related damage, depending on the particular step. In some implementations, the cooled substrate support may be used in a process to preferentially deposit a material (in some cases a reactant) on certain portions of the substrate.Type: GrantFiled: August 21, 2017Date of Patent: March 29, 2022Assignee: Lam Research CorporationInventors: Thorsten Lill, Ivan L. Berry, III, Anthony Ricci
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Publication number: 20220069218Abstract: A method for fabricating a plurality of resistive random access memory (RRAM) cells includes providing a substrate including a memory medium arranged on an underlying layer; creating channel holes in the memory medium having a first critical dimension in a range from 1 nm to 20 nm; depositing switching material defining a filament of the RRAM cells in the channel holes; depositing a top electrode of the RRAM cells on the memory medium and the switching material; and separating adjacent ones of the RRAM cells by etching the top electrode and the memory medium between adjacent ones of the channel holes.Type: ApplicationFiled: January 13, 2020Publication date: March 3, 2022Inventors: Hyungsuk YOON, Thorsten LILL, Yang PAN
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Patent number: 11239420Abstract: Methods and apparatuses for forming an encapsulation bilayer over a chalcogenide material on a semiconductor substrate are provided. Methods involve forming a bilayer including a barrier layer directly on chalcogenide material deposited using pulsed plasma plasma-enhanced chemical vapor deposition (PP-PECVD) and an encapsulation layer over the barrier layer deposited using plasma-enhanced atomic layer deposition (PEALD). In various embodiments, the barrier layer is formed using a halogen-free silicon precursor and the encapsulation layer deposited by PEALD is formed using a halogen-containing silicon precursor and a hydrogen-free nitrogen-containing reactant.Type: GrantFiled: August 24, 2018Date of Patent: February 1, 2022Assignee: Lam Research CorporationInventors: James Samuel Sims, Andrew John McKerrow, Meihua Shen, Thorsten Lill, Shane Tang, Kathryn Merced Kelchner, John Hoang, Alexander Dulkin, Danna Qian, Vikrant Rai
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Publication number: 20210391355Abstract: A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.Type: ApplicationFiled: October 22, 2019Publication date: December 16, 2021Inventors: Thorsten LILL, Meihua SHEN, John HOANG, Hui-Jung WU, Gereng GUNAWAN, Yang PAN
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Patent number: 11171021Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.Type: GrantFiled: November 17, 2015Date of Patent: November 9, 2021Assignee: Lam Research CorporationInventors: Harmeet Singh, Thorsten Lill, Alex Paterson, Richard A. Marsh, Saravanapriyan Sriraman
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Publication number: 20210280433Abstract: Disclosed are apparatuses and methods for performing atomic layer etching. A method may include modifying one or more surface layers of material on the substrate and exposing the one or more modified surface layers on the substrate to an electron source thereby removing, without using a plasma, the one or more modified surface layers on the substrate. An apparatus may include a processing chamber, a process gas unit, an electron source, and a controller with instructions configured to cause the process gas unit to flow a first process gas to a substrate in a chamber interior, the first process gas is configured to modify one or more layers of material on the substrate, and to cause the electron source to generate electrons and expose the one or more modified surface layers on the substrate to the electrons, the one or more modified surface layers being removed, without using a plasma.Type: ApplicationFiled: July 3, 2019Publication date: September 9, 2021Applicant: Lam Research CorporationInventors: Ivan L. Berry, III, Thorsten Lill, Andreas Fischer
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Patent number: 11062920Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.Type: GrantFiled: January 25, 2018Date of Patent: July 13, 2021Assignee: Lam Research CorporationInventors: Ivan L. Berry, III, Thorsten Lill
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Patent number: 11056322Abstract: A method for dry processing a substrate in a processing chamber is provided. The substrate is placed in the processing chamber. The substrate is dry processed, wherein the dry processing creates at least one gas byproduct. A concentration of the at least one gas byproduct is measured. The concentration of the at least one gas byproduct is used to determine processing rate of the substrate.Type: GrantFiled: August 3, 2017Date of Patent: July 6, 2021Assignee: Lam Research CorporationInventors: Yassine Kabouzi, Luc Albarede, Andrew D. Bailey, III, Jorge Luque, Seonkyung Lee, Thorsten Lill