Abstract: Disclosed are methods of adjusting the emission of vacuum ultraviolet (VUV) radiation from a plasma in a semiconductor processing chamber. The methods may include generating a plasma in the processing chamber which includes a VUV-emitter gas and a collisional energy absorber gas, and adjusting the emission of VUV radiation from the plasma by altering the concentration ratio of the VUV-emitter gas to collisional energy absorber gas in the plasma. In some embodiments, the VUV-emitter gas may be helium and the collisional energy absorber gas may be neon, and in certain such embodiments, adjusting VUV emission may include flowing helium and/or neon into the processing chamber in a proportion so as to alter the concentration ratio of helium to neon in the plasma. Also disclosed are apparatuses which implement the foregoing methods.

Abstract: Provided are methods of forming ashable hard masks (AHMs) with high etch selectivity and low hydrogen content using plasma enhanced chemical vapor deposition. Methods involve exposing a first layer to be etched on a semiconductor substrate to a carbon source and sulfur source, and generating a plasma to deposit a sulfur-doped AHM or amorphous carbon-based film on the first layer.

Abstract: An EFEM useful for transferring wafers to and from wafer processing modules comprises an enclosure having a controlled environment therein bounded by a front wall, a back wall, first and second side walls, a top wall, and a bottom wall. The first side wall and the second side wall include two or more wafer load ports wherein each wafer load port is adapted to receive a FOUP. The front wall includes wafer ports configured to attach to respective load locks operable to allow a wafer to be transferred to a front wall cluster processing tool. The back wall includes a wafer port adapted to be in operational relationship with a back wall cluster processing tool. A robot in the EFEM enclosure is operable to transfer wafers through the wafer load ports, the first front wall wafer port, the second front wall wafer port, and the back wall wafer port.

Abstract: Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

Abstract: A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed H2 containing gas and providing a pulsed halogen containing gas, wherein the pulsed H2 containing gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed H2 containing gas has an H2 high flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the H2 high flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.

Abstract: Provided herein are methods and apparatuses for cleaning wafers by coating an active surface of the wafer with a film of water to clean the wafer, delivering gas from a gas nozzle to the center of the active surface to break a film of water on the active surface to form a wet-dry boundary while spinning the wafer, and moving the gas nozzle radially outward from the center to the edge of the active surface of the wafer by following the wet-dry boundary. Tracking devices, such as cameras or charge-coupled devices, and systems may be used with an apparatus for cleaning wafers by tracking the wet-dry boundary on the wafer to move the gas nozzle to follow the wet-dry boundary. Cleaning apparatuses provided herein may be integrated with etching tools.

Abstract: Systems and method include providing a non-volatile random access memory (NVRAM) stack including a plurality of layers. The plurality of layers includes a dielectric layer and a metal layer. The metal layer of the NVRAM stack is patterned. The patterning causes damage to lateral side portions of the dielectric layer. The lateral portions of the dielectric layer are repaired by depositing dielectric material on the lateral side portions of the dielectric layer.

Abstract: The embodiments herein relate to methods and apparatus for performing ion etching on a semiconductor substrate, as well as methods for forming such apparatus. In some embodiments, an electrode assembly may be fabricated, the electrode assembly including a plurality of electrodes having different purposes, with each electrode secured to the next in a mechanically stable manner. Apertures may be formed in each electrode after the electrodes are secured together, thereby ensuring that the apertures are well-aligned between neighboring electrodes. In some cases, the electrodes are made from degeneratively doped silicon, and the electrode assembly is secured together through electrostatic bonding. Other electrode materials and methods of securing may also be used. The electrode assembly may include a hollow cathode emitter electrode in some cases, which may have a frustoconical or other non-cylindrical aperture shape. A chamber liner and/or reflector may also be present in some cases.

Abstract: Various embodiments herein relate to methods and apparatus for etching feature on a substrate. In a number of embodiments, no substrate rotation or tilting is used. While conventional etching processes rely on substrate rotation to even out the distribution of ions over the substrate surface, various embodiments herein achieve this purpose by moving the ion beams relative to the ion source. Movement of the ion beams can be achieved in a number of ways including electrostatic techniques, mechanical techniques, magnetic techniques, and combinations thereof.

Abstract: One process that may be used to remove material from a surface is ion etching. In certain cases, ion etching involves delivery of both ions and a reactive gas to a substrate. The disclosed embodiments permit local high pressure delivery of reactive gas to a substrate while maintaining a much lower pressure on portions of the substrate that are outside of the local high pressure delivery area. The low pressure is achieved by confining the high pressure reactant delivery to a small area and vacuuming away excess reactants and byproducts as they leave this small area and before they enter the larger substrate processing region. The disclosed techniques may be used to increase throughput while minimizing deleterious collisions between ions and other species present in the substrate processing region.

Abstract: Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.

Abstract: A method for etching a stack with an Ru containing layer disposed below a hardmask and above a magnetic tunnel junction (MTJ) stack with pinned layer is provided. The hardmask is etched with a dry etch. The Ru containing layer is etched, where the etching uses hypochlorite and/or O3 based chemistries. The MTJ stack is etched. The MTJ stack is capped with dielectric materials. The pinned layer is etched following the MTJ capping.

Abstract: The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds.

Abstract: A method for etching a stack with an Ru containing layer disposed below a hardmask and above a magnetic tunnel junction (MTJ) stack with pinned layer is provided. The hardmask is etched with a dry etch. The Ru containing layer is etched, where the etching uses hypochlorite and/or O3 based chemistries. The MTJ stack is etched. The MTJ stack is capped with dielectric materials. The pinned layer is etched following the MTJ capping.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.

Abstract: A method for etching a stack with at least one metal layer in one or more cycles is provided. An initiation step is preformed, transforming part of the at least one metal layer into metal oxide, metal halide, or lattice damaged metallic sites. A reactive step is performed providing one or more cycles, where each cycle comprises providing an organic solvent vapor to form a solvated metal, metal halide, or metal oxide state and providing an organic ligand solvent to form volatile organometallic compounds. A desorption of the volatile organometallic compounds is performed.

Abstract: A machined ceramic article having an initial surface defect density and an initial surface roughness is provided. The machined ceramic article is heated to a temperature range between about 1000° C. and about 1800° C. at a ramping rate of about 0.1° C. per minute to about 20° C. per minute. The machined ceramic article is heat-treated in air atmosphere. The machined ceramic article is heat treated at one or more temperatures within the temperature range for a duration of up to about 24 hours. The machined ceramic article is then cooled at the ramping rate, wherein after the heat treatment the machined ceramic article has a reduced surface defect density and a reduced surface roughness.

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: A machined ceramic article having an initial surface defect density and an initial surface roughness is provided. The machined ceramic article is heated to a temperature range between about 1000° C. and about 1800° C. at a ramping rate of about 0.1° C. per minute to about 20° C. per minute. The machined ceramic article is heat-treated in air atmosphere. The machined ceramic article is heat treated at one or more temperatures within the temperature range for a duration of up to about 24 hours. The machined ceramic article is then cooled at the ramping rate, wherein after the heat treatment the machined ceramic article has a reduced surface defect density and a reduced surface roughness.