Abstract: In one embodiment, a cell of an integrated circuit includes a master-slave flip-flop and comparator logic having inputs adapted to receive an input signal of the master-slave flip-flop, an inverted input signal of the master-slave flip-flop, an output signal of the master-slave flip-flop, and an inverted output signal of the master-slave flip-flop. The master-slave flip-flop comprises a master flip-flop and a slave flip-flop. The slave flip-flop includes a first inverting element and a second inverting element. An output of the first inverting element is connectable to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element. To output the output signal and the inverted output signal of the master-slave flip-flop, the output and the input of the second inverting element are connectable to the inputs of the comparator logic.

Abstract: A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

Abstract: An integrated circuit and a standard cell of an integrated circuit, having a master-slave flip-flop, having a comparator logic at whose inputs the input signal of the master-slave flip-flop, the inverted input signal of the master-slave flip-flop, the output signal of the master-slave flip-flop, and the inverted output signal of the master-slave flip-flops are present, wherein the master-slave flip-flop has a master flip-flop and a slave flip-flop, wherein the slave flip-flop has a first inverting element and a second inverting element. Whereby for feedback, an output of the first inverting element is connected to an input of the second inverting element and an output of the second inverting element to an input of the first inverting element.

Abstract: A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. In an apparatus for measuring a peak value of an analog voltage, an analog to digital converter is connected to receive an input voltage. A voltage level detection unit detects a voltage level of a received input voltage, and a digital memory receives and stores the detected voltage level. The digital memory updates the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Abstract: A technique for measuring peak voltages is provided that may be used in RF transceivers or receivers of wireless local area network systems. An apparatus is provided for measuring a peak value of an analog voltage. The apparatus comprises an analog to digital converter that is connected to receive an input voltage. The analog to digital converter comprises a voltage level detection unit that detects a voltage level of the received input voltage, and a digital memory that is connected for receiving and storing the detected voltage level. The digital memory is adapted for updating the stored voltage level only if the currently detected voltage level is higher, or lower, than the stored level. A digital code is output that corresponds to the stored voltage level. The provided technique may allow for a more simple and less complex implementation.

Abstract: A wireless local area network transceiver, an integrated circuit chip, a PLL (Phase Locked Loop) device and a method are provided that may reduce influences of switching noise. The frequency of an output signal of the PLL device is divided in a prescaler of the PLL device by a prescaler factor. The prescaler is operable in at least two modes with each mode having assigned a different prescaler factor. An accumulator is implemented in the PLL circuit for generating a mode switching signal for changing the mode of the prescaler. The generation of the mode switching signal is done by storing an accumulator value and processing a modulus function for updating the accumulator value. The provided technique may allow for reducing disturbances caused by switching the mode of the prescaler in the PLL circuit.

Abstract: A PLL frequency synthesizer able to automatically set an appropriate operating mode of the voltage controlled oscillator is provided. The voltage controlled oscillator is operable in a plurality of operating modes each defining a different operating frequency range of the voltage controlled oscillator. The appropriate operating mode is selected based on an error signal detected by a phase/frequency detector of the PLL frequency synthesizer. A window comparator is used for switching to adjacent operating modes if the error signal exceeds or falls below predefined upper and lower error voltage limits.

Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.

Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.