Patents by Inventor Thoru Mochizuki

Thoru Mochizuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells
    Patent number: 4970686
    Abstract: A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.
    Type: Grant
    Filed: August 21, 1989
    Date of Patent: November 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Naruke, Thoru Mochizuki, Taira Iwase, Masamichi Asano