Patents by Inventor Thu V. Nguyen

Thu V. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reversing the effects of hot carrier injection and bias threshold instability in SRAMs
    Patent number: 10586588
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for detrapping charges in gate dielectrics in P-channel pull-up transistors and N-channel pull-down transistors in a portion of a static random access memory (SRAM) array due to hot carrier injection (HCI), negative bias temperature instability (NBTI) and positive bias instability (PBTI). This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 10, 2020
    Assignee: SYNOPSYS, INC.
    Inventors: Jamil Kawa, Thu V. Nguyen, Victor Moroz
  • Self-timed activation logic for memory
    Patent number: 6785184
    Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Thu V. Nguyen, Ruban Kanapathippillai
  • Self-timed activation logic for memory
    Publication number: 20030202399
    Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
    Type: Application
    Filed: April 25, 2003
    Publication date: October 30, 2003
    Inventors: Thu V. Nguyen, Ruban Kanapathippillai
  • Self-timed activation logic for memory
    Patent number: 6618313
    Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Thu V. Nguyen, Ruban Kanapathippillai
  • Self-timed activation logic for memory
    Publication number: 20020145932
    Abstract: A self timed logic circuit is used to generate a self timed memory clock to access data in a memory. The self timed memory clock has a periodic pulse which enables circuitry in the memory for a brief period of time over its pulse width. The amount of charge and voltage change, required on bit lines for resolving a bit of data stored in a memory cell during the pulse width of the self timed memory clock, is reduced by using a sensitive sense amplifier so that power can be conserved.
    Type: Application
    Filed: January 14, 2002
    Publication date: October 10, 2002
    Inventors: Thu V. Nguyen, Ruban Kanapathippillai