Patents by Inventor Thuan T. Vu
Thuan T. Vu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8780639Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: May 8, 2012Date of Patent: July 15, 2014Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20140104961Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: May 8, 2012Publication date: April 17, 2014Applicant: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Patent number: 8576630Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: May 8, 2012Date of Patent: November 5, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Patent number: 8559228Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: GrantFiled: March 16, 2010Date of Patent: October 15, 2013Assignee: Silicon Storage Technology, Inc.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20120257465Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: May 8, 2012Publication date: October 11, 2012Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Patent number: 8270213Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: December 7, 2010Date of Patent: September 18, 2012Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 8072815Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: December 10, 2010Date of Patent: December 6, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 8018773Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: GrantFiled: March 4, 2009Date of Patent: September 13, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 7969239Abstract: A novel capacitor for use in a charge pump circuit has a substrate with a planar surface. A first electrode is in a first plane spaced apart from the planar surface. A second electrode is adjacent to and is spaced apart from the first electrode in the first plane and is capacitively coupled thereto. A third electrode is in a second plane, spaced apart from the first plane and is capacitively coupled to the first electrode. A fourth electrode is adjacent to and spaced apart from the third electrode in the second plane and is capacitively coupled to the third electrode and capacitively coupled to the second electrode. The first and fourth electrodes are electrically connected together and the second and third electrodes are electrically connected together. In addition, a cylindrical shape electrode, and a great wall electrode, and charge pump capacitor-by-pattern-filling is disclosed.Type: GrantFiled: September 29, 2009Date of Patent: June 28, 2011Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Q. Nguyen, Thuan T. Vu, Anh Ly
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Publication number: 20110122693Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: December 7, 2010Publication date: May 26, 2011Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Publication number: 20110080790Abstract: An array of memory cells has a first side adjacent to a first column, a second side opposite the first side, a third side adjacent to a first row, and a fourth side opposite the third side. Each memory cell is connected to a bit line, a high voltage source, and a low voltage source. Reference cells, substantially the same as the memory cells, evenly spaced apart, are embedded in the array. A high voltage decoder is on the first side, connected to the memory cells and reference cells in the same row. A low voltage row decoder is on the second side, connected to the memory cells and reference cells in the same row. Sense amplifiers are on the third side, connected to the memory cells and to the reference cells.Type: ApplicationFiled: December 10, 2010Publication date: April 7, 2011Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 7848140Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: July 22, 2009Date of Patent: December 7, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 7839682Abstract: An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array.Type: GrantFiled: January 29, 2009Date of Patent: November 23, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Publication number: 20100254207Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.Type: ApplicationFiled: March 16, 2010Publication date: October 7, 2010Applicant: SILICON STORAGE TECHNOLOGY, INC.Inventors: Xian Liu, Michael James Heinz, Eugene Jinglun Tam, Michael K. Doan, Alexander Kotov, Tho Ngoc Dang, Jack Edward Frayer, Jung Hee Yun, Thuan T. Vu
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Publication number: 20100226181Abstract: A non-volatile memory device comprises an array of non-volatile memory cells arranged in a plurality of rows and columns. Each memory cell has a bit terminal for connection to a bit line, a high voltage terminal for connection to a high voltage source, and a low voltage terminal for connection to a low voltage source. The array has a first side adjacent to a first column of memory cells, and a second side opposite the first side, a third side adjacent to a first row of memory cells, and a fourth side opposite the third side. The memory device further comprises a plurality of columns of reference memory cells embedded in the memory array, with a plurality of reference cells in each row of the array of non-volatile memory cells, substantially evenly spaced apart from one another.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 7778080Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: August 28, 2008Date of Patent: August 17, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Publication number: 20100188900Abstract: An array of non-volatile memory cells is arranged in a plurality of rows and columns, wherein each memory cell has at least three terminals: a first terminal for the read out of the signal from the memory cell, a second terminal to which high voltage is supplied during certain operation, and a third terminal to which low voltage is supplied in all operations. The cells in the same column have a common bit line connected to the first terminal of memory cells in the same column. The array comprises a first and second sub arrays of memory cells arranged adjacent to one another in the same row. A first decoder is positioned to one side of the first sub array in the same row as the first sub array. A second decoder is positioned to another side of the second sub array in the same row as the second sub array. A first high voltage line is connected to the second decoder and to only the second terminal of the memory cells in the same row in the first sub array.Type: ApplicationFiled: January 29, 2009Publication date: July 29, 2010Inventors: Hieu Van Tran, Anh Ly, Hung Q. Nguyen, Thuan T. Vu
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Patent number: 7663921Abstract: Systems and methods are disclosed including memory cells arranged in sectors. In one exemplary implementation, each memory cell may include a top gate, a source, a top gate line coupling memory cells in a sector, and a word line coupling memory cells together. Moreover, the top gate line may be dynamically coupled to the word line. Other exemplary implementations may relate to drivers for driving the word line and/or top gate line, multilevel memory cell, and/or floating gate line features.Type: GrantFiled: November 7, 2008Date of Patent: February 16, 2010Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Publication number: 20090323415Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: ApplicationFiled: July 22, 2009Publication date: December 31, 2009Applicant: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu
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Patent number: 7626863Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.Type: GrantFiled: February 16, 2007Date of Patent: December 1, 2009Assignee: Silicon Storage Technology, Inc.Inventors: Hieu Van Tran, Hung Quoc Nguyen, Anh Ly, Sheng-Hsiung Hsueh, Sang Thanh Nguyen, Loc B. Hoang, Steve Choi, Thuan T. Vu