Patents by Inventor Thungoc Tran
Thungoc Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8860482Abstract: A phase-locked loop circuit includes an oscillator circuit that generates a clock signal. The oscillator circuit has gears. Each of the gears of the oscillator circuit corresponds to a respective frequency range of the clock signal. A gear control circuit includes a regulator circuit that provides a supply voltage to the oscillator circuit. Each of the gears of the oscillator circuit corresponds to a different supply voltage provided by the regulator circuit. The regulator circuit varies the supply voltage to change a selected one of the gears of the oscillator circuit. The gear control circuit varies the supply voltage for one of the gears of the oscillator circuit to adjust a frequency range of that gear of the oscillator circuit.Type: GrantFiled: June 14, 2013Date of Patent: October 14, 2014Assignee: Altera CorporationInventors: Xiong Liu, Thungoc Tran, Tim Tri Hoang, Wilson Wong
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Patent number: 8570197Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: November 24, 2010Date of Patent: October 29, 2013Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Publication number: 20110068845Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: November 24, 2010Publication date: March 24, 2011Inventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch ZaIiznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Patent number: 7848318Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: February 27, 2006Date of Patent: December 7, 2010Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Patent number: 7812659Abstract: A programmable logic device (“PLD”) or the like has a plurality of data transmitter channels. Certain circuitry is shared by the channels. The shared circuitry includes at least one phase-locked loop (“PLL”) circuit for producing a primary clock signal, and global frequency divider circuitry for producing at least one global secondary clock signal based on the primary signal. The primary and global secondary signal(s) are distributed to the channels. Each of the channels includes local frequency divider circuitry for producing at least one local secondary clock signal based on the primary signal. Each channel also includes selection circuitry for selecting either the global or local secondary signal(s) for use by clock utilization circuitry of the channel. The clock utilization circuitry may include serializer circuitry for converting data from parallel to serial form.Type: GrantFiled: May 10, 2006Date of Patent: October 12, 2010Assignee: Altera CorporationInventors: Sergey Shumarayev, Rakesh H Patel, William W Bereza, Tim Tri Hoang, Thungoc Tran
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Patent number: 7702011Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.Type: GrantFiled: February 23, 2006Date of Patent: April 20, 2010Assignee: Altera CorporationInventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Simardeep Maangat, Wilson Wong, Rakesh Patel
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Patent number: 7697600Abstract: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.Type: GrantFiled: July 14, 2005Date of Patent: April 13, 2010Assignee: Altera CorporationInventors: Simardeep Maangat, Sergey Shumarayev, Wilson Wong, ThuNgoc Tran
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Patent number: 7659838Abstract: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: GrantFiled: February 21, 2006Date of Patent: February 9, 2010Assignee: Altera CorporationInventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Yuryevich Shumarayev, Arch Zaliznyak, Tim Tri Hoang, Ramanand Venkata, Chong Lee
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Multi-channel communication circuitry for programmable logic device integrated circuits and the like
Patent number: 7656187Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.Type: GrantFiled: November 28, 2005Date of Patent: February 2, 2010Assignee: Altera CorporationInventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Tim Tri Hoang, Ning Xue, Chong Lee, Ramanand Venkata -
Patent number: 7355449Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.Type: GrantFiled: February 1, 2006Date of Patent: April 8, 2008Assignee: Altera CorporationInventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Kazi Asaduzzaman, Wilson Wong, Mei Luo, Rakesh Patel
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Patent number: 7304507Abstract: Circuitry for distributing signals such as reference clock signals among blocks of transceiver circuitry on an integrated circuit such as a field programmable gate array (“FPGA”) employs bidirectional buffers rather than unidirectional buffers. This allows all buffers to have the same construction regardless of physical location, which facilitates construction of the circuitry using identical or substantially identical modules. The same approach may be used for distributing other types of signals among the transceiver blocks. For example, this approach may be used for distributing calibration control signals.Type: GrantFiled: November 28, 2005Date of Patent: December 4, 2007Assignee: Altera CorporationInventors: Thungoc Tran, Sergey Yuryevich Shumarayev, Tim Tri Hoang
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Patent number: 7276936Abstract: A programmable logic device includes high-speed serial interface (“HSSI”) circuitry that employs one or more clock signals. In addition to use of these clock signals in the HSSI circuitry, circuitry is provided for allowing at least one of these signals to be distributed throughout the PLD core circuitry, e.g., for use as an additional clock signal in the PLD core. Clock distribution is preferably done in a low-skew way.Type: GrantFiled: September 29, 2005Date of Patent: October 2, 2007Assignee: Altera CorporationInventors: Tim Tri Hoang, Sergey Yuryevich Shumarayev, In Whan Kim, Thungoc Tran
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Multi-channel communication circuitry for programmable logic device integrated circuits and the like
Publication number: 20070058618Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.Type: ApplicationFiled: November 28, 2005Publication date: March 15, 2007Inventors: Thungoc Tran, Sergey Shumarayev, Tim Hoang, Ning Xue, Chong Lee, Ramanand Venkata -
Publication number: 20070041455Abstract: Serial data signal receiver circuitry for inclusion on a PLD includes a plurality of equalizer circuits that are connected in series and that are individually controllable so that collectively they can compensate for a wide range of possible input signal attenuation characteristics. Other circuit features may be connected in relation to the equalizer circuits to give the receiver circuitry other capabilities. For example, these other features may include various types of loop-back test circuits, controllable termination resistance, controllable common mode voltage, and a controllable threshold for detection of an input signal. Various aspects of control of the receiver circuitry may be programmable.Type: ApplicationFiled: February 23, 2006Publication date: February 22, 2007Inventors: Thungoc Tran, Sergey Shumarayev, Simardeep Maangat, Wilson Wong, Rakesh Patel
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Publication number: 20070043991Abstract: Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: February 21, 2006Publication date: February 22, 2007Inventors: Toan Nguyen, Thungoc Tran, Sergey Shumarayev, Arch Zaliznyak, Tim Hoang, Ramanand Venkata, Chong Lee
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Publication number: 20070030184Abstract: Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).Type: ApplicationFiled: February 27, 2006Publication date: February 8, 2007Inventors: Toan Thanh Nguyen, Thungoc Tran, Sergey Shumarayev, Arch Zaliznyak, Shoujun Wang, Ramanand Venkata, Chong Lee
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Publication number: 20070014344Abstract: Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Inventors: Simardeep Maangat, Sergey Shumarayev, Wilson Wong, ThuNgoc Tran
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Publication number: 20070013411Abstract: High speed transmitter drivers and other types of driver circuitry may be required to produce output signals with variable slew rates. Driver circuitry and methods for providing variable slew rate control are described. Pre-driver circuitry with variable slew-rate may be used to supply signals with variable slew rate at the driver input. The driver and/or pre-driver circuits may include transistors with variable drive strengths. The driver and/or pre-driver circuits may also include selectably enabled stages for varying the circuit drive strength. The pre-driver circuitry may be delay matched to maintain signal quality. Other circuitry and methods are also described.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Inventors: Kazi Asaduzzaman, Sergey Shumarayev, Thungoc Tran, Wilson Wong, Rakesh Patel
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Patent number: 6556502Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.Type: GrantFiled: April 26, 2002Date of Patent: April 29, 2003Assignee: Altera CorporationInventors: Tony Ngai, Nitin Prasad, Thungoc Tran
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Publication number: 20020126562Abstract: A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.Type: ApplicationFiled: April 26, 2002Publication date: September 12, 2002Applicant: Altera CorporationInventors: Tony Ngai, Nitin Prasad, Thungoc Tran