Abstract: The invention relates to a method for lubricating a component consisting of a hydrophilic compound crosslinked by means of a water-soluble transition metal chelate.

Abstract: Methods and systems for scheduling virtual meetings across multiple geographic locations. In an example, the technology relates to a method for scheduling a virtual meeting. The method includes receiving configurations for location attributes and cross-geographic preferences for a plurality of users; storing the received configurations in a data storage; receiving, from a meeting organizer client device, a request for location attributes and cross-geographic preferences for one or more attendees of a virtual meeting; accessing, from the data storage, the requested location attributes and cross-geographic preferences for the one or more attendees; generating, based on at least the requested location attributes and cross-geographic preferences, a meeting time recommendation; and transmitting the accessed location attributes, cross-geographic preferences, and the generated meeting time recommendation to the meeting organizer client device.

Abstract: The invention relates to a method for lubricating a component consisting of a hydrophilic compound crosslinked by means of a water-soluble transition metal chelate.

Abstract: The present invention relates to compounds of general formula (1): in which, independently of each other, R1 and R2 represent: —OH, or —CH2—O—R3, or —CH2—S—R3, or R3, R4, R5 and R6 representing, independently of each other, —H or a carbon-containing group with 1 to 10 carbon atoms, saturated or unsaturated, optionally substituted with one or more heteroatomic groups. The invention also relates to pharmaceutical compositions containing these compounds, and their uses, in particular in the context of the treatment of cancer.

Abstract: The present invention relates to compounds of general formula (1): in which, independently of each other, R1 and R2 represent: —OH, or —CH2—O—R3, or —CH2—S—R3, or R3, R4, R5 and R6 representing, independently of each other, —H or a carbon-containing group with 1 to 10 carbon atoms, saturated or unsaturated, optionally substituted with one or more heteroatomic groups. The invention also relates to pharmaceutical compositions containing these compounds, and their uses, in particular in the context of the treatment of cancer.

Abstract: The present invention relates to compounds of general formula (1): in which, independently of each other, R1 and R2 represent: —OH, or —CH2—O—R3, or —CH2—S—R3, or R3, R4, R5 and R6 representing, independently of each other, —H or a carbon-containing group with 1 to 10 carbon atoms, saturated or unsaturated, optionally substituted with one or more heteroatomic groups. The invention also relates to pharmaceutical compositions containing these compounds, and their uses, in particular in the context of the treatment of cancer.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material (317).

Abstract: A semiconductor device has two types of multi-gate transistors, N channel and P channel, in which each type has a bottom gate and a top gate. The bottom gate and the top gate of the N channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the N channel transistors. Similarly, the bottom gate and the top gate of the P channel transistors are chosen to be of a metal or metals that are for optimizing the performance of the P channel transistors.

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract: A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.

Abstract: A method of generating a layout of one or more planar double gate transistors can include generating a single gate transistor layout at least in part from one or more double gate transistor circuits, logic diagrams, or any combination thereof, and generating the planar double gate transistor layout at least in part from the single gate transistor layout. The method is highly flexible regarding the generation and adjusting of gate shapes and gate contact shapes to ensure the proper connection of the gates to voltage or signal lines, and when such generation, adjusting, or any combination thereof is performed. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.

Abstract: A method of automatically generating planar double gate transistor shapes can include taking an integrated circuit layout design that includes single gate transistors, locating the gate shapes and active shapes for the transistors, generating top gate shapes, planar double gate active shapes, bottom gate shapes, active cavity shapes, source/drain cavity shapes, and top gate contact shapes, bottom gate contact shapes, thru-gate contact shapes, and source/drain contact shapes for the planar double gate transistors. The method can generate gate contact shapes that have top and bottom gates to be electrically connected within the same planar double gate transistor or separate gate contact shapes where the top and bottom gates are not electrically connected to each other. In one embodiment, a data processing system can include a program that has code in the form of instructions to carry out the method.

Abstract: Double gate transistors (12, 13) having different bottom gate dielectric thicknesses are formed on a first wafer (101) by forming a first gate dielectric layer (107); removing part of the first gate dielectric layer (107) from a first area (60); forming a second gate dielectric layer (108) to obtain a thinner bottom gate dielectric layer (150) over the first area (60) and a thicker bottom gate dielectric layer (151) over the second area (70); and forming a planar bottom gate layer (109) over first and second gate dielectric layers. After inverting and bonding the first wafer (101) to a second wafer (103), the bottom gate electrodes (109-2, 109-3), bottom gate dielectric layers (107, 108) and channel regions (203-2, 203-3) for the first and second double gate transistors (12, 13) are selectively etched prior to formation of the top gate structures.

Abstract: A semiconductor fabrication process includes forming a sacrificial layer on a substrate of a donor wafer and implanting hydrogen ions into the substrate through the sacrificial layer to create a stress layer in the substrate. After forming the stress layer, multiple layer stacks are formed on the donor wafer substrate including a bottom gate conductor layer and a bottom gate dielectric layer. An upper surface of the donor wafer is bonded to an upper surface of a handle wafer. An oxide or low-k layer may be formed on the handle wafer. A portion of the substrate of the donor wafer is then cleaved. The bottom gate conductor layer is selected from the group including polysilicon, alpha silicon, alpha germanium, W, Ti, Ta, TiN, and TaSiN.

Abstract: Methods are provided for forming a semiconductor device from a substrate comprising a bottom gate layer, a channel layer overlying the bottom gate layer, and a top gate structure formed over the channel layer. First, a hardmask comprising a first material interposed between a second material and a third material is deposited over a portion of the top gate structure. Then, the hardmask and top gate structure are encapsulated with an insulating material to form a spacer. A channel structure is formed from the channel layer, and the channel structure is disposed under the spacer. A bottom gate structure is formed from the bottom gate layer, and the bottom gate structure is disposed under the channel structure. Then, a source/drain contact is formed around the bottom gate structure.

Abstract: A method for treating exposed metal in a semiconductor wafer (301) in wafer processing is disclosed herein. In accordance with the method, a wafer is provided which is equipped with a metal layer (307) and a substrate (303), wherein a portion of the metal layer is exposed at the edge of the wafer. The exposed portion of the metal layer is then covered with a dielectric material (317).

Abstract: A transistor having a bottom gate formed from a layer of gate material and a channel region formed from a layer semiconductor material. In some examples, the layer of gate material is patterned separately from the layer of semiconductor material. In some examples the patterning of the layer of gate material also leaves other conductive structures that may be, in some examples, used to provide a bottom gate bias voltage to the bottom gate. In some examples, the layer of semiconductor material is formed by bonding two wafers together with a substrate of one of the wafers being cleaved, wherein a remaining portion of the semiconductor substrate is a semiconductor layer from which the channel region is formed.