Patents by Inventor Tiago N. Santos

Tiago N. Santos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10169104
    Abstract: As disclosed herein, a method, executed by a computer, includes comparing a current power consumption profile for a computing task with an historical power consumption profile, receiving a request for a computing resource, granting the request if the historical power consumption profile does not suggest a pending peak in the current power consumption profile or the historical power consumption profile indicates persistent consumption at a higher power level, and denying the request for the computing resource if the historical power consumption profile suggests a pending peak in the current power consumption profile and the historical power consumption profile indicates temporary consumption at the higher power level. Denying the request may include initiating an allocation timeout and subsequently ending the allocation timeout in response to a drop in a power consumption below a selected level. A computer system and computer program product corresponding to the method are also disclosed herein.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rafael C. S. Folco, Breno H. Leitao, Thiago C. Rotta, Tiago N. Santos
  • Patent number: 9891964
    Abstract: As disclosed herein a method, executed by a computer, for providing improved multi-protocol traffic processing includes receiving a data packet, determining if a big processor is activated, deactivating a little processor and activating the big processor if the big processor is not activated and an overflow queue is full, and deactivating the big processor and activating the little processor if the big processor is activated and a current throughput for the big processor is below a first threshold or a sustained throughput for the big processor remains below a second threshold. The big and little processors may be co-located on a single integrated circuit. An overflow queue, managed with a token bucket algorithm, may be used to enable the little processor to handle short burst of data packet traffic. A computer program product and an apparatus corresponding to the described method are also disclosed herein.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Murilo O. Araujo, Leonardo R. Augusto, Rafael C. S. Folco, Breno H. Leitao, Tiago N. Santos
  • Patent number: 9886331
    Abstract: As disclosed herein a method, executed by a computer, for providing improved multi-protocol traffic processing includes receiving a data packet, determining if a big processor is activated, deactivating a little processor and activating the big processor if the big processor is not activated and an overflow queue is full, and deactivating the big processor and activating the little processor if the big processor is activated and a current throughput for the big processor is below a first threshold or a sustained throughput for the big processor remains below a second threshold. The big and little processors may be co-located on a single integrated circuit. An overflow queue, managed with a token bucket algorithm, may be used to enable the little processor to handle short burst of data packet traffic. A computer program product and an apparatus corresponding to the described method are also disclosed herein.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Murilo O. Araujo, Leonardo R. Augusto, Rafael C. S. Folco, Breno H. Leitao, Tiago N. Santos
  • Patent number: 9634895
    Abstract: Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset, including: determining, by a NIC control module, an amount of network traffic being processed by the NIC; determining, by the NIC control module, whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring, by the NIC control module, the NIC to utilize the high performance media access control chipset for data communications operations; and responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring, by the NIC control module, the NIC to utilize the low performance media access control chipset for data communications operations.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rafael C. Folco, Breno H. Leitão, Tiago N. Santos
  • Patent number: 9628333
    Abstract: Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset, including: determining, by a NIC control module, an amount of network traffic being processed by the NIC; determining, by the NIC control module, whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring, by the NIC control module, the NIC to utilize the high performance media access control chipset for data communications operations; and responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring, by the NIC control module, the NIC to utilize the low performance media access control chipset for data communications operations.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 18, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rafael C. Folco, Breno H. Leitão, Tiago N. Santos
  • Publication number: 20160139970
    Abstract: As disclosed herein a method, executed by a computer, for providing improved multi-protocol traffic processing includes receiving a data packet, determining if a big processor is activated, deactivating a little processor and activating the big processor if the big processor is not activated and an overflow queue is full, and deactivating the big processor and activating the little processor if the big processor is activated and a current throughput for the big processor is below a first threshold or a sustained throughput for the big processor remains below a second threshold. The big and little processors may be co-located on a single integrated circuit. An overflow queue, managed with a token bucket algorithm, may be used to enable the little processor to handle short burst of data packet traffic. A computer program product and an apparatus corresponding to the described method are also disclosed herein.
    Type: Application
    Filed: December 11, 2014
    Publication date: May 19, 2016
    Inventors: Murilo O. Araujo, Leonardo R. Augusto, Rafael C. S. Folco, Breno H. Leitao, Tiago N. Santos
  • Publication number: 20160140070
    Abstract: As disclosed herein a method, executed by a computer, for providing improved multi-protocol traffic processing includes receiving a data packet, determining if a big processor is activated, deactivating a little processor and activating the big processor if the big processor is not activated and an overflow queue is full, and deactivating the big processor and activating the little processor if the big processor is activated and a current throughput for the big processor is below a first threshold or a sustained throughput for the big processor remains below a second threshold. The big and little processors may be co-located on a single integrated circuit. An overflow queue, managed with a token bucket algorithm, may be used to enable the little processor to handle short burst of data packet traffic. A computer program product and an apparatus corresponding to the described method are also disclosed herein.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 19, 2016
    Inventors: Murilo O. Araujo, Leonardo R. Augusto, Rafael C. S. Folco, Breno H. Leitao, Tiago N. Santos
  • Publication number: 20160139963
    Abstract: As disclosed herein, a method, executed by a computer, includes comparing a current power consumption profile for a computing task with an historical power consumption profile, receiving a request for a computing resource, granting the request if the historical power consumption profile does not suggest a pending peak in the current power consumption profile or the historical power consumption profile indicates persistent consumption at a higher power level, and denying the request for the computing resource if the historical power consumption profile suggests a pending peak in the current power consumption profile and the historical power consumption profile indicates temporary consumption at the higher power level. Denying the request may include initiating an allocation timeout and subsequently ending the allocation timeout in response to a drop in a power consumption below a selected level. A computer system and computer program product corresponding to the method are also disclosed herein.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 19, 2016
    Inventors: Rafael C. S. Folco, Breno H. Leitao, Thiago C. Rotta, Tiago N. Santos
  • Publication number: 20150365286
    Abstract: Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset, including: determining, by a NIC control module, an amount of network traffic being processed by the NIC; determining, by the NIC control module, whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring, by the NIC control module, the NIC to utilize the high performance media access control chipset for data communications operations; and responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring, by the NIC control module, the NIC to utilize the low performance media access control chipset for data communications operations.
    Type: Application
    Filed: August 25, 2015
    Publication date: December 17, 2015
    Applicant: International Business Machines Corporation
    Inventors: Rafael C. FOLCO, Breno H. LEITÃO, Tiago N. SANTOS
  • Publication number: 20150154141
    Abstract: Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset, including: determining, by a NIC control module, an amount of network traffic being processed by the NIC; determining, by the NIC control module, whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring, by the NIC control module, the NIC to utilize the high performance media access control chipset for data communications operations; and responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring, by the NIC control module, the NIC to utilize the low performance media access control chipset for data communications operations.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: International Business Machines Corporation
    Inventors: Rafael C. Folco, Breno H. Leitão, Tiago N. Santos
  • Publication number: 20150134126
    Abstract: A method for diverting water flow of a drainage system is provided. The method comprises receiving monitored information from a plurality of sensors of a drainage system. In one aspect, the drainage system includes at least one valve to control water flow of the drainage system, and wherein the plurality of sensors and the at least one valve are communicatively connected to a controller of the drainage system. Moreover, the method comprises analyzing the monitored information of the plurality of sensors to resolve a maximum flow problem of water flow of the drainage system. The method further comprises identifying a path through the drainage system to divert water flow of the drainage system based on the resolved maximum flow problem. The method further comprises controlling a plurality of valves to divert the water flow in the drainage system based on the identified path of the drainage system.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Leonardo R. Augusto, Anibal C. Carvalho, Tiago N. Santos, Paulo R. Vital, José R. Ziviani