Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

Abstract: A random data generation circuit includes: a first shift register and a second shift register. The first shift register includes n output ends Q1 to Qn, the second shift register includes n output ends Qn+1 to Q2n, and each of the output ends outputs 1-bit data in a clock cycle of a clock signal; and a parallel-to-serial circuit, coupled to the output ends Q1 to Q2n and configured to convert parallel data output from Q1 to Q2n in a clock cycle into serial data for output. An initial value of the first shift register is different from an initial value of the second shift register. Data may be generated in parallel by using two shift registers, and the parallel data generated by the two shift registers is converted into serial data by using the parallel-to-serial circuit to be output.

Abstract: A delay circuit includes a self-shielding circuit and a delay. The self-shielding circuit is configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N?1 second initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases. The delay is electrically connected to the self-shielding circuit and is configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal. Thus, the accuracy of signal processing can be improved.

Abstract: A circuit and method for testing a memory chip are provided. The circuit for testing a memory chip includes: a data reading apparatus configured to read word line data stored in all banks of a tested memory; a first comparison module, configured to receive word line data stored in one tested word line, perform a comparison test on each bit data in the word line data stored in the tested word line, and output a first test result; a second comparison module, configured to receive the first test results of all the tested word lines in one bank, and compress the first test results into a second test result; a third comparison module, configured to receive the second test result of each bank, and compress all the second test results into an N-bit final test result; and a register apparatus configured to read and save the final test result.

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Abstract: A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

Abstract: Disclosed are a test method for self-refresh frequency of a memory array and a memory array test device. The test method includes: providing a memory array; determining a shortest duration for charge in memory cells of the memory array to leak off, and marking the shortest duration as a first duration; setting an auto-refresh cycle of the memory array according to the first duration, where the auto-refresh cycle is longer than the first duration; performing m tests, where an nth test includes sequentially performing the following: refresh position count resetting, writing preset data to the memory array, performing a self-refresh having a duration of Tn, performing an auto-refresh having a duration of one auto-refresh cycle, reading the memory array, and recording a read status, where Tn?1<Tn, and 2?n?m.

Abstract: The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.

Abstract: Disclosed are a test method for self-refresh frequency of a memory array and a memory array test device. The test method includes: providing a memory array; determining a shortest duration for charge in memory cells of the memory array to leak off, and marking the shortest duration as a first duration; setting an auto-refresh cycle of the memory array according to the first duration, where the auto-refresh cycle is longer than the first duration; performing m tests, where an nth test includes sequentially performing the following: refresh position count resetting, writing preset data to the memory array, performing a self-refresh having a duration of Tn, performing an auto-refresh having a duration of one auto-refresh cycle, reading the memory array, and recording a read status, where Tn?1<Tn, and 2?n?m.

Abstract: A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Abstract: The present disclosure provides a method, a device and a terminal for testing a memory chip. The method may include setting an attack mode and random attack parameters, generating a random attack command according to the attack mode and random attack parameters, attacking the memory chip according to the random attack command, and testing the attacked memory chip and generating a test result. This method is able to simulate various types of attacks and can thus perform a suitable test on the memory chip for the types of the actual attack. In addition, since the attacks can be randomized to any memory cell of the memory chip, testing of the whole memory chip is made possible.